FIR-PARA-XP-N1 Datasheet FIR-PARA-XP-N1 | P7-P9

Lattice Semiconductor Parallel FIR Filter User’s Guide

Figure 4. Timing for Multi-cycle (3 Cycles), Real or Complex-parallel Mode

Complex-serial Mode

The data and handshake signals for a typical complex-serial mode conﬁguration (C = 3) are shown in Figure 5.

Every input data cycle has a real data cycle followed by an imaginary data cycle. Each of these real and imaginary

data cycles is C clock cycles wide. The irdy input signal must be asserted high during the ﬁrst cycle of every input

data cycle.

The output data cycles also contain a real data cycle followed by an imaginary data cycle. The ordy output signal

goes high during the ﬁrst clock cycle of every output real or imaginary data cycle. The real_out output signal

goes high during the ﬁrst clock cycle of every output real data cycle.

Figure 5. Timing for Multi-cycle (3 Cycles), Complex-serial Mode

internal data

processing

irdy

clk

din

dout

ordy

clk

din 1r

irdy

r 2i

dout

ordy

real_out

xxxx

internal data

processing

Lattice Semiconductor Parallel FIR Filter User’s Guide

Decimation

Decimation is downsampling of the data stream. In a simple decimation ﬁlter with decimation ratio ‘D’, every D

sample of the input is sent to the output. The danger with downsampling is that aliasing can occur if the input signal

is not band-limited to 1/D of the original bandwidth. Therefore, to prevent aliasing, it is necessary to do a lowpass

ﬁltering before downsampling. The decimation ﬁlter implementation is, therefore, a cascade of a lowpass ﬁlter and

a downsampler. The implementation of this is similar to a normal FIR, except that D - 1 samples are skipped at the

output, after every valid output. The output data rate is 1/D

of the input rate. The arithmetic resources are reused

in this design, as it is not necessary to compute an output for every input sample.

The output signal, ordy, goes high during the ﬁrst cycle of each data output. For, complex-serial mode, there is an

additional output, real_out, which goes high during the ﬁrst cycle of every real part of the complex data.

The timing diagrams for two decimation ﬁlter implementations are shown in Figures 6 and 7.

Figure 6. Timing for Real or Complex-parallel, Decimation Mode (Ratio = 3)

Figure 7. Timing for Complex-serial, Decimation Mode (Ratio = 3)

Interpolation

Interpolation is the reverse process of decimation. In this mode, the data is upsampled. For an interpolation ratio U,

U - 1 ‘zeros’ are introduced between any two consecutive samples and the resulting expanded stream is passed

through a lowpass ﬁlter. The operational environment of an interpolation ﬁlter is similar to a regular FIR ﬁlter, except

clk

din

6 7

internal data

processing

dout

ordy

internal data

processing

clk

din

1r 1i

2i 3r

4r 4i

irdy

6r 6i

7r 7i

dout

ordy

real_out

Lattice Semiconductor Parallel FIR Filter User’s Guide

the input data rate is reduced by ‘U’ and 0’s are introduced in the taps. The timing diagrams for two Interpolation Fil-

ter implementations are shown in Figures 8 and 9.

Figure 8. Timing for Real or Complex-parallel, Interpolation Mode (Ratio = 3)

Figure 9. Timing for Complex-serial, Interpolation Mode (Ratio = 3)

Output Scaling and Rounding

When the user deﬁned output width (OW) of the ﬁlter is less than the full output width of the ﬁlter (OFW), the out-

puts are scaled using a rounding scheme that is based on the parameter “rounding method”. If the rounding

method is deﬁned as “truncation”, the least signiﬁcant OFW-OW bits are simply discarded and the most signiﬁcant

OW bits are retained in the output. If the rounding method is selected to be “nearest”, the most signiﬁcant OW bits

are retained and they are rounded based on the value of the least signiﬁcant bits that are discarded. Truncation

takes the value to the next step towards minus inﬁnity and rounding nearest takes the value to the nearest step in

either direction.

Table 3 illustrates the output scaling and rounding for two numbers using integer, ﬁxed point, signed and unsigned

representations. In the example, the full output width (OFW) is 8 and the desired output width (OW) is 6. Output

scaling in this case is equivalent to a division by 4.

clk

din

1 2 3

2a 2b 2c

internal data

processing

dout

2b 2c

1b 3a

clk

din

irdy

2r 2i

1b 1c 2b

dout

1ar 1ai

1br

1bi

1cr

1ci

2ar

2ai

xxx

real_out

internal data

processing

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