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70V658S10BC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
©2008 Integrated Device Technology, Inc.
1
OCTOBER 2008
DSC-4869/7
CE
0R
R/
W
R
CE
1R
BE
0R
BE
1R
BE
2R
BE
3R
128/64/32K x 36
MEMORY
ARRAY
Address
Decoder
A
16R
(1)
A
0R
Address
Decoder
CE
0L
R/
W
L
CE
1L
BE
0L
BE
1L
BE
2L
BE
3L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
B
E
0
L
B
E
1
L
B
E
2
L
B
E
3
L
B
E
3
R
B
E
2
R
B
E
1
R
B
E
0
R
I/O
0L-
I/O
35L
A
16 L
(1)
A
0L
I/O
0R -
I/O
35R
Di n_L
ADDR_L
Di n_R
ADDR_R
OE
R
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM
L
INT
L
(3)
BUSY
L
(2,3)
M/S
R/W
L
OE
L
R/W
R
OE
R
CE
0L
CE
1L
CE
0R
CE
1R
BUSY
R
(2,3)
SEM
R
INT
R
(3)
TMS
TCK
TRST
TDI
TDO
JTAG
4869 drw 01
Functional Block Diagram
◆◆
◆◆
◆
Full on-chip hardware support of semaphore signaling
between ports
◆◆
◆◆
◆
Fully asynchronous operation from either port
◆
Separate byte controls for multiplexed bus and bus
matching compatibility
◆◆
◆◆
◆
Supports JTAG features compliant to IEEE 1149.1
◆◆
◆◆
◆
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
◆◆
◆◆
◆
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
◆◆
◆◆
◆
Available in a 208-pin Plastic Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
◆◆
◆◆
◆
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆◆
◆◆
◆
Green parts available, see ordering information
Features
◆◆
◆◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆◆
◆◆
◆
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
◆◆
◆◆
◆
Dual chip enables allow for depth expansion without
external logic
◆◆
◆◆
◆
IDT70V659/58/57 easily expands data bus width to 72 bits
or more using the Master/Slave select when cascading
more than one device
◆◆
◆◆
◆
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆◆
◆◆
◆
Busy and Interrupt Flags
◆◆
◆◆
◆
On-chip port arbitration logic
HIGH-SPEED 3.3V
128/64/32K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
IDT70V659/58/57S
1. A16 is a NC for IDT70V658. Also, Addresses A16 and A15 are NC's for IDT70V657.
2. BUSY is an input as a Slave (M/S=V
IL) and an output when it is a Master (M/S=VIH).
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
NOTES:
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT70V659/58/57 is a high-speed 128/64/32K x 36 Asynchro-
nous Dual-Port Static RAM. The IDT70V659/58/57 is designed to be used
as a stand-alone 4/2/1Mbit Dual-Port RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either CE
0 or CE1) permit the
on-chip circuitry of each port to enter a very low standby power mode.
The 70V659/58/57 can support an operating voltage of either 3.3V
or 2.5V on one or both ports, controlled by the OPT pins. The power supply
for the core of the device (VDD) remains at 3.3V.
3
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Configurations
(3,4,5,6,7,8)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
7
3
7
4
7
5
7
6
7
7
7
8
7
9
8
0
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
9
0
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
1
0
0
1
0
1
1
0
2
1
0
3
1
0
4
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
2
0
8
2
0
7
2
0
6
2
0
5
2
0
4
2
0
3
2
0
2
2
0
1
2
0
0
1
9
9
1
9
8
1
9
7
1
9
6
1
9
5
1
9
4
1
9
3
1
9
2
1
9
1
1
9
0
1
8
9
1
8
8
1
8
7
1
8
6
1
8
5
1
8
4
1
8
3
1
8
2
1
8
1
1
8
0
1
7
9
1
7
8
1
7
7
1
7
6
1
7
5
1
7
4
1
7
3
1
7
2
1
7
1
1
7
0
1
6
9
1
6
8
1
6
7
1
6
6
1
6
5
1
6
4
1
6
3
1
6
2
1
6
1
1
6
0
1
5
9
1
5
8
1
5
7
70V659/58/57DR
DR-208
(7)
208-Pin PQFP
Top View
(8)
I/O
19L
I/O
19R
I/O
20L
I/O
20R
V
DDQL
V
SS
I/O
21L
I/O
21R
I/O
22L
I/O
22R
V
DDQR
V
SS
I/O
23L
I/O
23R
I/O
24L
I/O
24R
V
DDQL
V
SS
I/O
25L
I/O
25R
I/O
26L
I/O
26R
V
DDQR
V
SS
V
DD
V
DD
V
SS
V
SS
V
DDQL
V
SS
I/O
27R
I/O
27L
I/O
28R
I/O
28L
V
DDQR
V
SS
I/O
29R
I/O
29L
I/O
30R
I/O
30L
V
DDQL
V
SS
I/O
31R
I/O
31L
I/O
32R
I/O
32L
V
DDQR
V
SS
I/O
33R
I/O
33L
I/O
34R
I/O
34L
V
S
S
V
D
D
Q
L
I
/
O
3
5
R
I
/
O
3
5
L
V
D
D
T
M
S
T
C
K
T
R
S
T
N
C
N
C
N
C
A
1
6
R
(
1
)
A
1
5
R
(
2
)
A
1
4
R
A
1
3
R
A
1
2
R
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
B
E
3
R
B
E
2
R
B
E
1
R
B
E
0
R
C
E
1
R
C
E
0
R
V
D
D
V
D
D
V
S
S
V
S
S
S
E
M
R
O
E
R
R
/
W
R
B
U
S
Y
R
I
N
T
R
M
/
S
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
V
D
D
V
S
S
V
S
S
O
P
T
R
I
/
O
0
L
I
/
O
0
R
V
D
D
Q
L
V
S
S
I/O
16L
I/O
16R
I/O
15L
I/O
15R
V
SS
V
DDQL
I/O
14L
I/O
14R
I/O
13L
I/O
13R
V
SS
V
DDQR
I/O
12L
I/O
12R
I/O
11L
I/O
11R
V
SS
V
DDQL
I/O
10L
I/O
10R
I/O
9L
I/O
9R
V
SS
V
DDQR
V
DD
V
DD
V
SS
V
SS
V
SS
V
DDQL
I/O
8R
I/O
8L
I/O
7R
I/O
7L
V
SS
V
DDQR
I/O
6R
I/O
6L
I/O
5R
I/O
5L
V
SS
V
DDQL
I/O
4R
I/O
4L
I/O
3R
I/O
3L
V
SS
V
DDQR
I/O
2R
I/O
2L
I/O
1R
I/O
1L
V
S
S
V
D
D
Q
R
I
/
O
1
8
R
I
/
O
1
8
L
V
S
S
V
D
D
T
D
I
T
D
O
N
C
N
C
N
C
A
1
6
L
(
1
)
A
1
5
L
(
2
)
A
1
4
L
A
1
3
L
A
1
2
L
A
1
1
L
A
1
0
L
A
9
L
A
8
L
A
7
L
B
E
3
L
B
E
2
L
B
E
1
L
B
E
0
L
C
E
1
L
C
E
0
L
V
D
D
V
D
D
V
S
S
V
S
S
S
E
M
L
O
E
L
R
/
W
L
B
U
S
Y
L
I
N
T
L
N
C
A
6
L
A
5
L
A
4
L
A
3
L
A
2
L
A
1
L
A
0
L
V
D
D
V
D
D
V
S
S
O
P
T
L
I
/
O
1
7
L
I
/
O
1
7
R
V
D
D
Q
R
V
S
S
4869 drw 02a
03/19/04
NOTES:
1. Pin is a NC for IDT70V658 and IDT70V657.
2. Pin is a NC for IDT70V657.
3. All V
DD pins must be connected to 3.3V power supply.
4. All V
DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (3.3V) and 2.5V if OPT pin for that port is
set to V
SS (0V).
5. All V
SS pins must be connected to ground.
6. Package body is approximately 28mm x 28mm x 3.5mm.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

70V658S10BC

Mfr. #:
Buy 70V658S10BC
Manufacturer:
IDT
Description:
SRAM 64Kx36 STD-PWR, 3.3V DUAL-PORT RAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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