NB3L208K
www.onsemi.com
12
Signal and Feature Operation
Table 6. OE# FUNCTIONALITY
(Notes 35, 36 and 37)
CLK_IN / CLK_IN# OE# (Pin) DIF DIF # Notes
Running 1 Low Low 35
Running 0 Running Running
Not Running x x x
35.The outputs are tri−stated, but the termination networks pull them low
36.OE# pins are asynchronous asserted−low signals.
37.Each OE# pin controls two pair of DIF outputs.
OE# Assertion (Transition from ‘1’ to ‘0’)
All differential outputs that were tri−stated (low due to
termination pull down) will resume normal operation in a
glitch free manner. The latency from the assertion to active
outputs is 4 − 12 DIF clock periods.
Note: Input clock must remain running for a minimum of
12 clock cycles.
OE# De−Assertion (Transition from ‘0’ to ‘1’)
The maximum latency from the de−assertion to tristated
(low due to termination pull down) outputs is 12 DIF clock
periods.
Table 7. NB3L208K RESISTIVE LUMPED TEST LOADS FOR DIFFERENTIAL CLOCKS
Board Target Trace/Term Z Reference R, Iref = VDD/(3*R
REF
) Output Current V
OH
@ Z Rs Rp
100 W Differential
50 W Single−Ended
R
REF
= 475 W 1%,
I
REF
= 2.32 mA
I
OH
= 6 * I
REF
0.7 V @ 50
33 W
5%
50 W
5%
85 W Differential
43 W Single−Ended
R
REF
= 412 W, 1%,
I
REF
= 2.67 mA
I
OH
= 6 * I
REF
0.7V @ 43.2
27 W
5%
43 W
5%
ORDERING INFORMATION
Device Package Shipping
†
NB3L208KMNG QFN32
(Pb−Free)
74 Units / Rail
NB3L208KMNTXG QFN32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
