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LTM4624EY#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
LTM4624
13
4624fc
For more information www.linear.com/LTM4624
applicaTions inForMaTion
RUN Enable
Pulling the RUN pin to ground forces the LTM4624 into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Bringing the RUN pin
above 0.7V turns on the internal reference only, while still
keeping the power MOSFETs off. Increasing the RUN pin
voltage above 1.25V will turn on the entire chip.
Pre-Biased Output Start-Up
There may be situations that require the power supply to
start up with some charge on the output capacitors. The
LTM4624 can safely power up into a pre-biased output
without discharging it.
The LTM4624 accomplishes this by forcing discontinuous
mode (DCM) operation until the TRACK/SS pin voltage
reaches 0.6V reference voltage. This will prevent the BG
from turning on during the pre-biased output start-up
which would discharge the output.
Do not pre-bias LTM4624 with an output voltage above
INTV
CC
voltage (3.3V) or set voltage by FB resistor which-
ever is lower.
Overtemperature Protection
The internal overtemperature protection monitors the junc
-
tion temperature of the module. If the junction temperature
reac
hes approximately 160°C, both power switches will be
turned off until the temperature drops about 15°C cooler.
Low Input Application
The LTM4624 module has a separate SV
IN
pin which
makes it suitable for low input voltage applications down
to 2.375V. The SV
IN
pin is the single input of the whole
control circuitry while the V
IN
pin is the power input which
directly connects to the drain of the top MOSFET. In most
applications where V
IN
is greater than 4V, connect SV
IN
directly to V
IN
with a short trace. An optional filter, con-
sisting of a resistor (1Ω to 10Ω) between SV
IN
and V
IN
along with a 0.1µF bypass capacitor between SV
IN
and
ground, can be placed for additional noise immunity. This
filter is not necessary in most cases if good PCB layout
practices are followed (see Figure 19). In a low input
voltage (2.375V to 4V) application, or to reduce power
dissipation by the internal bias LDO, connect SV
IN
to an
external voltage higher than 4V with a 0.1µF local bypass
capacitor. Figure 21 shows an example of a low input
voltage application. Please note the SV
IN
voltage cannot
go below the V
OUT
voltage.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param
-
eters defined by JESD 51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients is
found in JESD 51-12 (Guidelines for Reporting and Using
Electronic Package Thermal Information).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their ap
-
plication at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con
-
figuration section are, in and of themselves, not relevant to
providing guidance of thermal per
formance; instead, the
derating cur
ves provided in this data sheet can be used
in a manner that yields insight and guidance pertaining to
one’s application usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section gives four thermal coeffi
-
cients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased below:
1.
θ
JA
, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo
-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
LTM4624
14
4624fc
For more information www.linear.com/LTM4624
applicaTions inForMaTion
2. θ
JCbottom
, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the pack
-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages, but the test
conditions
don’t
generally match the user’s application.
3. θ
JCtop
, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top of
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ
JCbottom
, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θ
JB
, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance
where almost all of the heat flows through the bottom
of the µModule package and into the board, and is really
the sum of the θ
JCbottom
and the thermal resistance of
the bottom of the part through the solder joints and
through a portion of the board. The board temperature
is measured a specified distance from the package.
A graphical representation of the aforementioned ther
-
mal resistances is given in Figure 5; blue resistances are
contained within the μModule regulator
, whereas green
resistances are external to the µModule package.
As
a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a μModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot
-
tom of the µModule package—as the standard defines
for θ
JCtop
and θ
JCbottom
, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4624 be aware there are multiple power
devices and components dissipating power, with a con
-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled environment chamber
to reasonably define and correlate the thermal resistance
Figure 5. Graphical Representation of JESD 51-12 Thermal Coefficients
4624 F05
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE
LTM4624
15
4624fc
For more information www.linear.com/LTM4624
applicaTions inForMaTion
values supplied in this data sheet: (1) Initially, FEA software
is used to accurately build the mechanical geometry of
the LTM4624 and the specified PCB with all of the correct
material coefficients along with accurate power loss source
definitions; (2) this model simulates a software-defined
JEDEC environment consistent with JSED 51-12 to predict
power loss heat flow and temperature readings at different
interfaces that enable the calculation of the JEDEC-defined
thermal resistance values; (3) the model and FEA software
is used to evaluate the LTM4624 with heat sink and airflow;
(4) having solved for and analyzed these thermal resistance
values and simulated various operating conditions in the
software model, a thorough laboratory evaluation replicates
the simulated conditions with thermocouples within a
controlled environment chamber while operating the device
at the same power loss as that which was simulated. An
outcome of this process and due diligence yields the set
of derating curves shown in this data sheet. After these
laboratory tests have been performed and correlated to
the LTM4624 model, then the θ
JB
and θ
BA
are summed
together to provide a value that should closely equal the
θ
JA
value because approximately 100% of power loss
flows from the junction through the board into ambient
with no airflow or top mounted heat sink.
The 1.0V, 1.5V, 3.3V and 5V power loss curves in Figures6
to 9 can be used in coordination with the load current
derating curves in Figures 10 to 16 for calculating an
approximate θ
JA
thermal resistance for the LTM4624
with various airflow conditions. The power loss curves
are taken at room temperature, and are increased with a
multiplicative factor according to the ambient tempera
-
ture. This approximate factor is: 1.4 for 120°C at junction
temperature. Maximum
load current is achievable while
increasing ambient temperature as long as the junction
temperature is less than 120°C, which is a 5°C guard band
from maximum junction temperature of 125°C. When the
ambient temperature reaches a point where the junction
temperature is 120°C, then the load current is lowered to
maintain the junction at 120°C while increasing ambient
temperature up to 120°C. The derating curves are plotted
with the output current starting at 4A and the ambient tem
-
perature at 30°C. The output voltages are 1.0V, 1.5V, 3.3V
and 5V. These are chosen to include the lower and higher
output voltage ranges for correlating the thermal resistance.
Thermal models are derived from several temperature
measurements in a controlled temperature chamber along
with thermal modeling analysis. The junction temperatures
are monitored while ambient temperature is increased
with and without airflow. The power loss increase with
ambient temperature change is factored into the derating
curves. The junctions are maintained at 120°C maximum
while lowering output current or power with increasing
ambient temperature. The decreased output current will
decrease the internal module loss as ambient temperature
is increased. The monitored junction temperature of 120°C
minus the ambient operating temperature specifies how
much module temperature rise can be allowed. As an
example, in Figure11 the load current is derated to ~3A at
~95°C with no air flow or heat sink and the power loss for
the 12V to 1.0V at 3A output is about 1.15W. The 1.15W
loss is calculated with the ~0.82W room temperature loss
from the 12V to 1.0V power loss curve at 3A, and the 1.4
multiplying factor at 120°C junction temperature. If the 95°C
ambient temperature is subtracted from the 120°C junction
temperature, then the difference of 25°C divided by 1.15W
equals a 22°C/W θ
JA
thermal resistance. Table 2 specifies
a 22°C/W value which is very close. Table 3, Table4 and
Table 5 provide equivalent thermal resistances for 1.5V
3.3V and 5V outputs with and without airflow and heat
sinking. The derived thermal resistances in Table 3, Table4
and Table 5 for the various conditions can be multiplied
by the calculated power loss as a function of ambient
temperature to derive temperature rise above ambient,
thus maximum junction temperature. Room temperature
power loss can be derived from the efficiency curves in the
Typical Performance Characteristics section and adjusted
with the above ambient temperature multiplicative factors.
The printed circuit board is a 1.6mm thick 4-layer board
with two ounce copper for the two outer layers and one
ounce copper for the two inner layers. The PCB dimen
-
sions are 95mm × 76mm.
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LTM4624EY#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 14VIN, 4A Step-Down DC/DC Module Regulator
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