18
FN9198.4
April 17, 2009
delay the output until the boost is enabled internally. The
delayed output appears at A
VDD
.
A
VDD
soft-starts at the beginning of the third ramp. The
soft-start ramp depends on the value of the C
DLY
capacitor.
For C
DLY
of 220nF, the soft-start time is ~9.6ms.
V
OFF
turns on at the start of the fourth peak. At the same
time, DELB gate goes low to turn on the external PMOS to
generate a delayed A
VDD
output.
V
ON
is enabled at the beginning of the sixth ramp.
Once the start-up sequence is complete, the voltage on the
C
DLY
capacitor remains at 1.15V until either a fault is
detected or the EN pin is disabled. If a fault is detected, the
voltage on C
DLY
rises to 2.4V at which point the chip is
disabled until the power is cycled or enable is toggled.
A
VDD_delay
Generation Using DELB
DELB pin is an open drain internal N-FET output used to
drive an external optional P-FET to provide a delayed A
VDD
supply which also has no initial pedistal voltage (see
Figure 14 and compare the A
VDD
and A
VDD_delayed
curves). When the part is enabled, the N-FET is held off until
C
DLY
reaches the 4th peak in the start-up sequence. During
this period, the voltage potential of the source and gate of
the external P-FET (M0 in application diagram) should be
almost the same due to the presence of the resistor (R4)
across the source and gate, hence M0 will be off. Please
note that the maximum leakage of DELB in this period is
500nA. To avoid any mis-trigger, the maximum value of R4
should be less than:
Where V
GS(th)_min(M0)
is the minimum value of gate
threshold voltage of M0.
After C
DLY
reaches the 4th peak, the internal N-FET is
turned-on and produces an initial current output of
IDELB_ON1 (~50µA). This current allows the user to control
the turn-on inrush current into the A
VDD_delay
supply
capacitors by a suitable choice of C4. This capacitor can
provide extra delay and also filter out any noise coupled into
the gate of M0, avoiding spurious turn-on, however, C4 must
not be so large that it prevents DELB reaching 0.6V by the
end of the start-up sequence on C
DLY
, else a fault time-out
ramp on C
DLY
will start. A value of 22nF is typically required
for C4. The 0.6V threshold is used by the chip's fault
detection system and if V(DELB) is still above 0.6V at the
end of the power sequencing then a fault time-out ramp will
be initiated on C
DLY
.
When the voltage at DELB falls below ~0.6V, it's current is
increased to IDELB_ON2 (~1.4mA) to firmly pull the DELB
voltage to ground.
If the maximum V
GS
voltage of M0 is less than the A
VDD
voltage being used, then a resistor may be inserted between
the DELB pin and the gate of M0 such that it's potential
divider action with R4 ensures the gate/source stays below
VGS(M0)max. This additional resistor allows much larger
values of C4 to be used, and hence longer A
VDD
delay,
without affecting the fault protection on DELB.
Component Selection for Start-up Sequencing and
Fault Protection
The C
REF
capacitor is typically set at 220nF and is required
to stabilize the V
REF
output. The range of C
REF
is from
22nF to 1µF and should not be more than five times the
capacitor on CDEL to ensure correct start-up operation.
The CDEL capacitor is typically 220nF and has a usable
range from 47nF minimum to several microfarads - only
limited by the leakage in the capacitor reaching µA levels.
CDEL should be at least 1/5 of the value of C
REF
(see
previous). Note, with 220nF on CDEL, the fault time-out will
be typically 50ms. and the use of a larger/smaller value will
vary this time proportionally (e.g. 1µF will give a fault time-
out period of typically 230ms).
Fault Sequencing
The ISL97650 has advanced overall fault detection systems
including Over Current Protection (OCP) for both boost and
buck converters, Under Voltage Lockout Protection (UVLP)
and Over-Temperature Protection.
Once the peak current flowing through the switching
MOSFET of the boost and buck converters triggers the
current limit threshold, the PWM comparator will disable the
output, cycle by cycle, until the current is back to normal.
The ISL97650 detects each feedback voltage of A
VDD
, V
ON
,
V
OFF
and V
LOGIC
. If any of the V
ON
, V
OFF
or A
VDD
feedback is lower than the fault threshold, then a timed fault
ramp will appear on CDEL. If it completes, then V
ON
, V
OFF
and A
VDD
will shut down, but V
LOGIC
will stay on.
If V
LOGIC
feedback is lower than fault threshold, then all
channels will switch off, and V
IN
or Enable needs recycling
to turn them on again.
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of +150°C, the device will shut
down. Operation with die temperatures between +125°C and
+150°C can be tolerated for short periods of time, however,
in order to maximize the operating life of the IC, it is
recommended that the effective continuous operating
junction temperature of the die should not exceed +125°C.
R
4_max
V
GS th_min(M0)
500nA
--------------------------------------------
(EQ. 24)
ISL97650
