4
FN9198.4
April 17, 2009
POSITIVE (V
ON
) CHARGE PUMP
V
ON
V
ON
Output Voltage Range 2X or 3X Charge Pump VSUP+
2V
34 V
ILoad_PCP_min External Load Driving Capability V
ON
= 25V (2X Charge Pump) 20 mA
V
ON
= 34V (3X Charge Pump) 20 mA
Ron(VSUP_SW) ON Resistance of V
SUP
Input Switch I(switch) = +40mA 10 17
Ron(C1/2-)H High-Side Driver ON-Resistance at
C1- and C2-
I(C1/2-) = +40mA 30
Ron(C1/2-)L Low-Side Driver ON-Resistance at
C1- and C2-
I(C1/2-) = -40mA 4 7
Ipu(VSUP_SW) Pull-Up Current Limit in V
SUP
Input
Switch
V(C2+) = 0V to V(SUP) - 0.4V - V(diode) 40 100 mA
Ipu(C1/2-) Pull-Up Current Limit in C1- and C2- V(C1/2-) = 0V to V(VSUP) - 0.4V 40 100 mA
Ipd(C1/2-) Pull-Down Current Limit in C1- and C2- V(C1/2-) = 0.2V to V(VSUP) -100 -40 mA
I(POUT)leak Leakage Current in P
OUT
EN = LOW -5 5 µA
V
FBP
FBP Regulation Voltage T
A
= +25°C 1.176 1.2 1.224 V
1.172 1.2 1.228 V
ACCP V
ON
Output Accuracy I
ON
= 1mA, T
A
= +25°C -2 +2 %
D_PCP_max Max Duty Cycle of the Positive Charge
Pump
50 %
V(diode) Internal Schottky Diode Forward Voltage I(diode) = +40mA 700 800 mV
ENABLE INPUTS
VHI-EN Enable “HIGH” 2.2 V
VLO_EN Enable “LOW” 0.8 V
IEN_pd Enable Pin Pull-Down Current V
EN
> VLO_EN 25 µA
VHI-ENL Logic Enable “HIGH” 2.2 V
VLO-ENL Logic Enable “LOW” 0.8 V
IENL_pd Logic Enable Pin Pull-Down Current V
ENL
> VLO_ENL 25 µA
V
ON
SLICE POSITIVE SUPPLY = V(POUT)
I(POUT)_slice V
ON
Slice Current from P
OUT
Supply CTL = VDD, sequence complete 200 400 µA
CTL = AGND, sequence complete 100 150 µA
RON(POUT-COM) ON-Resistance between P
OUT
- COM CTL = VDD, sequence complete 5 10
RON(DRN-COM) ON-Resistance between DRN - COM CTL = ACGND, sequence complete 30 60
RON_COM ON-Resistance between COM and
PGND3
200 500 1500
VLO CTL Input LOW Voltage 0.8 V
VHI CTL Input HIGH Voltage 2.2 V
FAULT DETECTION THRESHOLDS
T_off Thermal Shut-Down (latched and reset
by power cycle or EN cycle)
Temperature rising 150 °C
Vth_A
VDD
(FBB) A
VDD
Boost Short Detection V(FBB) falling less than 0.9 V
Electrical Specifications V
IN
= 12V, V
BOOST
= V
SUP
= 15V, V
ON
= 25V, V
OFF
= -8V, over-temperature from -40°C to +105°C, unless
otherwise stated. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
ISL97650
5
FN9198.4
April 17, 2009
Vth_V
LOGIC
(FBL) V
LOGIC
Buck Short Detection V(FBL) falling less than 0.9 V
Vth_POUT(FBP) P
OUT
Charge Pump Short Detection V(FBP) falling less than 0.9 V
Vth_NOUT(FBN) N
OUT
Charge Pump Short Detection V(FBN) rising more than 0.4 V
t
FD
Fault Delay Time to Chip Turns Off 52 ms
START-UP SEQUENCING
t
START-UP
Enable to A
VDD
Start Time C
DEL
= 220nF 80 ms
I
DELB_ON
DELB Pull-Down Current or Resistance
when Enabled by the Start-Up Sequence
VDELB > 0.9V 36 50 70 µA
VDELB < 0.9V 1.00 1.326 1.75 k
I
DELB_OFF
DELB Pull-Down Current or Resistance
when Disabled
VDELB < 20V 500 nA
C
DEL
Sequence Timing and Fault Time Out
Capacitor
10 220 nF
t
VOFF
A
VDD
to V
OFF
C
DEL
= 220nF 9 ms
t
VON
V
OFF
to V
ON
Delay C
DEL
= 220nF 20 ms
t
VON-SLICE
V
ON
to V
ON-SLICE
Delay C
DEL
= 220nF 17 ms
Electrical Specifications V
IN
= 12V, V
BOOST
= V
SUP
= 15V, V
ON
= 25V, V
OFF
= -8V, over-temperature from -40°C to +105°C, unless
otherwise stated. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Typical Performance Curves
FIGURE 1. BOOST EFFICIENCY
FIGURE 2. BOOST LOAD REGULATION
EFFICIENCY (%)
0
20
40
60
80
100
0 500 1000 1500
I
O
(mA)
V
IN
= 12V
V
IN
= 5V
V
IN
= 12V
V
IN
= 5V
0
0.02
0.04
0.06
0.08
0.10
0.12
0 500 1000 1500 2000
I
O
(mA)
LOAD REGULATION (%)
ISL97650
6
FN9198.4
April 17, 2009
FIGURE 3. BUCK EFFICIENCY FIGURE 4. BUCK LOAD REGULATION
FIGURE 5. V
OFF
LOAD REGULATION vs I
OFF
FIGURE 6. V
ON
LOAD REGULATION vs I
ON
FIGURE 7. BOOST DISCONTINUOUS MODE
FIGURE 8. THRESHOLD OF BOOST FROM DC TO CC MODE
Typical Performance Curves (Continued)
V
IN
= 12V
V
IN
= 5V
0
0 500 1000 1500 2000
I
O
(mA)
20
40
60
80
100
EFFICIENCY (%)
V
IN
= 12V
V
IN
= 5V
0 500 1000 1500 2000
I
O
(mA)
-2.0
-1.5
-1.0
-0.5
0
LOAD REGULATION (%)
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0 1020304050607080
I
OFF
(mA)
V
OFF
LOAD REGULATION (%)
V
OFF
= -8V
-0.35
-0.30
-0.20
-0.15
-0.10
-0.05
0
0 102030405060
I
ON
(mA)
V
ON
LOAD REGULATION (%)
V
ON
= 25V
-0.25
200ns/DIV
Ch1 = LX(boost)(5V/DIV)
Ch2 = Io(Boost)(10mA/DIV)
200ns/DIV
Ch1 = LX(boost)(5V/DIV)
Ch 2 = Io(Boost)(10mA/DIV)
ISL97650

ISL97650ARTZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Display Drivers & Controllers ISL97650ARTZ-T 4-CH INTEGRTD LCD SUPY
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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