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USBLC6-4SC6

P1-P3P4-P6P7-P9P10-P12P13-P13
Technical information USBLC6-4
4/13 DocID11068 Rev 7
2 Technical information
2.1 Surge protection
The USBLC6-4SC6 is particularly optimized to provide surge protection based on the rail to
rail topology.
The clamping voltage V
CL
can be calculated as follows:
V
CL
+ = V
TRANSIL
+ V
F
for positive surges
V
CL
- = - V
F
for negative surges
with: V
F
= V
T
+ R
d
.I
p
(V
F
forward drop voltage, V
T
forward drop threshold voltage
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically:
R
d
= 0.5 Ω and V
T
= 1.1 V.
For an IEC 61000-4-2 surge level 4 (Contact Discharge: V
g
= 8 kV, R
g
= 330 Ω),
V
BUS
= +5 V, and if in a first approximation, we assume that:
I
p
= V
g
/ R
g
= 24 A.
So, we find:
V
CL
+ = +31.2 V
V
CL
- = -13.1 V
Note: The calculations do not take into account phenomena due to parasitic inductances.
2.2 Surge protection application example
If we consider that the connections from the pin V
BUS
to V
CC
, from I/O to data line and from
GND to PCB GND plane are implemented as racks 10 mm long and 0.5 mm large, we can
assume that the parasitic inductances L
VBUS
L
I/0
and L
GND
of these tracks are about 6 nH.
So, when an IEC 61000-4-2 surge occurs, due to the rise time of this spike (t
r
= 1 ns), the
voltage V
CL
has an extra value equal to L
I/0
·dI/dt, + L
GND
·dI/dt
The dI/dt is calculated as:
dI/dt = I
p
/t
r
= 24 A/ns
The overvoltage due to the parasitic inductances is:
L
I/0
·dI/dt, = L
GND
·dI/dt = 6 x 24 = 144 V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be:
V
CL
+ = +31.2 + 144 + 144 = 319.2 V
V
CL
- = -13.1 - 144 -144 = -301.1 V
We can significantly reduce this phenomena with simple layout optimization. It is for this
reason that some recommendations have to be followed (see 2.3: How to ensure good ESD
protection).
DocID11068 Rev 7 5/13
USBLC6-4 Technical information
13
Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout
2.3 How to ensure good ESD protection
While the USBLC6-4SC6 provides high immunity to ESD surge, efficient protection depends
on the layout of the board. In the same way, with the rail to rail topology, the track from data
lines to I/O pins, from V
CC
to the V
BUS
pin and from GND plane to GND pin must be as short
as possible to avoid overvoltages due to parasitic phenomena (see Figure 7 and Figure 8
for layout considerations)
V
BUS
L
I/O
L
VBUS
L
GND
L
I/O
L
GND
Vpin
CC
V
CL
V
F
I/O pin
V
TRANSIL
V+V
TRANSIL F
-V
F
V
CL-
t = 1 ns
r
t
t
t = 1 ns
r
V
CL+
GND pin
Data line
Positive
Surge
Negative
Surge
ESD sur ge on data line
di
dt
L
I/O
+ L
GND
di
dt
di
dt
-L
I/O
- L
GND
di
dt
di
dt
V
+
=V +V + L + L
sur ge > 0
CL TRANSIL F I/O GND
V = -V - L - L
sur ge > 0
CL- F I/O GND
di
dt
di
dt
di
dt
di
dt
di
dt
Rd.IpVV
BR
TRANSIL
+=
Figure 7. ESD behavior: optimized layout and
addition of a capacitance of 100 nF
Figure 8. ESD behavior: measurement
conditions (with coupling capacitance)
Unsuitable layout
Optimized layout
TEST BOARD
V
bus
ESD SURGE
OUT
IN
USBLC6-4SC6
Technical information USBLC6-4
6/13 DocID11068 Rev 7
Note: The measurements have been done with the USBLC6-4SC6 in open circuit.
Important:
A good precaution to take is to put the protection device as close as possible to the
disturbance source (generally the connector).
2.4 Crosstalk behavior
2.4.1 Crosstalk phenomenon
Figure 11. Crosstalk phenomenon
The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12
or β21) increases when the gap across lines decreases, particularly in silicon dice. In the
above example the expected signal on load R
L2
is α
2
V
G2
, in fact the real voltage at this
point has got an extra value β
21
V
G1
. This part of the V
G1
signal represents the effect of the
crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into
account when the drivers impose fast digital data or high frequency analog signals in the
disturbing line. The perturbed line will be more affected if it works with low voltage signal or
high load impedance (few kΩ).
Figure 9. Remaining voltage after the USBLC6-
4SC6 during positive ESD surge
Figure 10. Remaining voltage after the USBLC6-
4SC6 during negative ESD surge
P1-P3P4-P6P7-P9P10-P12P13-P13

USBLC6-4SC6

Mfr. #:
Buy USBLC6-4SC6
Manufacturer:
STMicroelectronics
Description:
TVS Diodes / ESD Suppressors Low Cap ESD Protect
Lifecycle:
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