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ISL6554CBZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
10
FN9003.3
February 11, 2005
time. PGOOD also goes “low” during this time due to VSEN
going below its threshold voltage. To lower the average
output dissipation, the soft-start initial wait time is increased
from 32 to 2048 cycles, then the soft-start ramp is initiated.
At a PWM frequency of 200kHz, for instance, an overcurrent
detection would cause a dead time of 10.24ms, then a ramp
of 10.08ms.
At the end of the delay, PWM outputs are restarted and the
soft-start ramp is initiated. If a short is present at that time,
the cycle is repeated. This is the hiccup mode.
Figure 6 shows the supply shorted under operation and the
hiccup operating mode described above. Note that due to
the high short circuit current, overcurrent is detected before
completion of the start-up sequence so the delay is not quite
as long as the normal soft-start cycle.
CORE Voltage Programming
The voltage identification pins (VID0, VID1,VID2,VID3 and
VID4) set the CORE output voltage. Each VID pin is pulled to
VCC by an internal 20A current source and accepts open-
collector/open-drain/open-switch-to-ground or standard low-
voltage TTL or CMOS signals.
Table 1 shows the nominal DAC voltage as a function of the
VID codes. The power supply system is 1% accurate over
the operating temperature and voltage range.
Current Sensing and Balancing
Overview
The ISL6554 samples the on-state voltage drop across each
synchronous rectifier MOSFET, Q2, as an indication of the
inductor current in that phase (see Figure 7). Neglecting AC
effects (to be discussed later), the voltage drop across Q2 is
simply r
DS(ON)
(Q2) x inductor current (I
L
). Note that I
L
, the
inductor current, is either 1/2, 1/3, or 1/4 of the total current
(I
LT
), depending on how many phases are in use.
The voltage at Q2’s drain, the PHASE node, is applied to the
R
ISEN
resistor to develop the I
ISEN
current to the ISL6554
ISEN pin. This pin is held at virtual ground, so the current
through R
ISEN
is I
L
x r
DS(ON)
(Q2) / R
ISEN
.
The I
ISEN
current provides information to perform the
following functions:
1. Detection of an overcurrent condition
2. Balance the I
L
currents in multiple channels
Overcurrent, Selecting RISEN
The current detected through the R
ISEN
resistor is
averaged with the current(s) detected in the other 1, 2, or 3
channels. The averaged current is compared with a
trimmed,
internally generated current, and used to detect
an overcurrent condition.
TABLE 1. VOLTAGE IDENTIFICATION CODES
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VCC
CORE
(V
DC
)VID4 VID3 VID2 VID1 VID0
1 1111Output Off
1 11100.95
1 11010.975
1 11001.000
1 10111.025
1 10101.050
1 10011.075
1 10001.100
1 01111.125
PGOOD
SHORT
50A/DIV.
CURRENT
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
SUPPLY FREQUENCY = 200kHz, V
IN
= 12V
HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY
CORE LOAD CURRENT = 31A, 5V LOAD = 5A
SHORT APPLIED HERE
FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP
1 01101.150
1 01011.175
1 01001.200
1 00111.225
1 00101.250
1 00011.275
1 00001.300
0 11111.325
0 11101.350
0 11011.375
0 11001.400
0 10111.425
0 10101.450
0 10011.475
0 10001.500
0 01111.525
0 01101.550
0 01011.575
0 01001.600
0 00111.625
0 00101.650
0 00011.675
0 00001.700
TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued)
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VCC
CORE
(V
DC
)VID4 VID3 VID2 VID1 VID0
ISL6554
11
FN9003.3
February 11, 2005
The nominal current through the R
ISEN
resistor should be
50A at full output load current, and the nominal trip point for
overcurrent detection is 165% of that value, or 82.5A.
Therefore, R
ISEN
= I
L
x r
DS(ON)
(Q2) / 50A.
For a full load of 25A per phase, and an r
DS(ON)
(Q2) of
4m, R
ISEN
= 2k.
The overcurrent trip point would be 165% of 25A, or ~ 41A
per phase. The R
ISEN
value can be adjusted to change the
overcurrent trip point, but it is suggested to stay within 25%
of nominal.
Current Balancing
The detected currents are also used to balance the phase
currents.
Each phase’s current is compared to the average of all
phase currents, and the difference is used to create an offset
in that phase’s PWM comparator. The offset is in a direction
to reduce the imbalance.
The balancing circuit can not make up for a difference in
r
DS(ON)
between synchronous rectifiers. If a FET has a higher
r
DS(ON)
, the current through that phase will be reduced.
Figures 8 and 9 show the inductor current of a two phase
system without and with current balancing.
Inductor Current
The inductor current in each phase of a multi-phase Buck
converter has two components. There is a current equal to
the load current divided by the number of phases (I
LT
/ n),
and a sawtooth current, (i
PK-PK
) resulting from switching.
The sawtooth component is dependent on the size of the
inductors, the switching frequency of each phase, and the
values of the input and output voltage. Ignoring secondary
effects, such as series resistance, the peak to peak value of
the sawtooth current can be described by:
i
PK-PK
= (V
IN
x V
CORE
- V
CORE
2
) / (L x F
SW
x V
IN
)
Where: V
CORE
= DC value of the output or V
ID
voltage
V
IN
= DC value of the input or supply voltage
L= value of the inductor
F
SW
= switching frequency
Example: For V
CORE
= 1.6V,
V
IN
= 12V,
L= 1.3H,
F
SW
= 250kHz,
Then i
PK-PK
= 4.3A
The inductor, or load current, flows alternately from V
IN
through Q1 and from ground through Q2. The ISL6554
samples the on-state voltage drop across each Q2 transistor
to indicate the inductor current in that phase. The voltage
drop is sampled 1/3 of a switching period, i/F
SW
, after Q1 is
turned OFF and Q2 is turned on. Because of the sawtooth
current component, the sampled current is different from the
average current per phase. Neglecting secondary effects,
the sampled current (I
SAMPLE
) can be related to the load
current (I
LT
) by:
I
SAMPLE
=
I
LT
/ n +
(V
IN
V
CORE
-3V
CORE
2
) / (6L x F
SW
x V
IN
)
Where: I
LT
= total load current
n = the number of channels
Example: Using the previously given conditions, and
For I
LT
= 100A,
n = 4
Then I
SAMPLE
= 25.49A
FIGURE 7. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING
CURRENT
SENSING
COMPARATOR
PWM
CIRCUIT
AVERAGING
CURRENT
FROM
OTHER
CHANNELS
SAWTOOTH
GENERATOR
+
DIFFERENCE
R
ISEN
+
CORRECTION
ERROR
AMPLIFIER
FB
COMP
REFERENCE
TO OTHER
CHANNELS
ISEN
R
IN
R
FB
C
c
V
CORE
Q1
Q2
COMPARATOR
REFERENCE
TO OVER
CURRENT
TRIP
L
01
PHASE
INDUCTOR
CURRENT(S)
FROM
OTHER
CHANNELS
PWM
I
L
DAC
ISL6554
C
OUT
R
LOAD
V
IN
ONLY ONE OUTPUT
HIP6601
-
-
STAGE SHOWN
SENSING
+
-
+
-
+
-
ISL6554
12
FN9003.3
February 11, 2005
As discussed previously, the voltage drop across each Q2
transistor at the point in time when current is sampled is r
DSON
(Q2) x
I
SAMPLE
. The voltage at Q2’s drain, the PHASE node,
is applied through the R
ISEN
resistor to the ISL6554 ISEN pin.
This pin is held at virtual ground, so the current into ISEN is:
I
SENSE
= I
SAMPLE
x r
DS(ON)
(Q2) / R
ISEN
.
R
Isen
= I
SAMPLE
x r
DS(ON)
(Q2) / 50A
Example: From the previous conditions,
where I
LT
= 100A,
I
SAMPLE
= 25.49A,
r
DS(ON)
(Q2) = 4m
Then: R
ISEN
= 2.04K and
I
CURRENT TRIP
= 165%
Short circuit I
LT
= 165A.
Channel Frequency Oscillator
The channel oscillator frequency is set by placing a resistor,
R
T
, to ground from the FS/DIS pin. Figure 10 is a curve
showing the relationship between frequency, F
SW
, and
resistor R
T
. To avoid pickup by the FS/DIS pin, it is important
to place this resistor next to the pin.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting impedances
and parasitic circuit elements. These voltage spikes can
degrade efficiency, radiate noise into the circuit and lead to
device overvoltage stress. Careful component layout and
printed circuit design minimizes the voltage spikes in the
converter. Consider, as an example, the turnoff transition of
the upper PWM MOSFET. Prior to turnoff, the upper MOSFET
was carrying channel current. During the turnoff, current stops
flowing in the upper MOSFET and is picked up by the lower
MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes. Contact Intersil for evaluation
board drawings of the component placement and printed
circuit board.
There are two sets of critical components in a DC-DC
converter using a ISL6554 controller and a HIP6601 gate
driver. The power components are the most critical because
they switch large amounts of energy. Next are small signal
components that connect to sensitive nodes or supply critical
bypassing current and signal coupling.
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors, C
IN
,
and the power switches. Locate the output inductors and
output capacitors between the MOSFETs and the load.
Locate the gate driver close to the MOSFETs.
The critical small components include the bypass capacitors for
VCC and PVCC on the gate driver ICs. Locate the bypass
capacitor, C
BP
, for the ISL6554 controller close to the device. It
is especially important to locate the resistors associated with
the input to the amplifiers close to their respective pins, since
they represent the input to feedback amplifiers. Resistor R
T
,
that sets the oscillator frequency should also be located next to
the associated pin. It is especially important to place the R
SEN
resistors at the respective terminals of the ISL6554.
A multi-layer printed circuit board is recommended. Figure 11
shows the connections of the critical components for one
output channel of the converter. Note that capacitors C
IN
and
C
OUT
could each represent numerous physical capacitors.
Dedicate one solid layer, usually the middle layer of the PC
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the metal runs from
the PHASE terminal to output inductor short. The power plane
should support the input power and output power nodes. Use
0
5
10
15
20
25
AMPERES
FIGURE 8. TWO CHANNEL MULTI-PHASE SYSTEM WITH
CURRENT BALANCING DISABLED
0
5
10
15
20
25
AMPERES
FIGURE 9. TWO CHANNEL MULTI-PHASE SYSTEM WITH
CURRENT BALANCING ENABLED
ISL6554
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ISL6554CBZ

Mfr. #:
Buy ISL6554CBZ
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 20L 2-4 PHS 0 95V-1 7V VID PWM BUCK CONT
Lifecycle:
New from this manufacturer.
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