8
FN6798.2
October 16, 2015
.subckt comp1 out inp inm vss
e1 out vss table { (v(inp) v(inm))* 5000} (0,0) (3.2,3.2)
Rout out vss 10meg
Rinp inp vss 10meg
Rinm inm vss 10meg
.ends comp1
Application Guidelines
It is important to minimize inductance to the power FET by
keeping the output drive current loop as short as possible.
Also, the decoupling capacitor, Cq, should be a high quality
ceramic capacitor with a Q that should be a least 10x the
gate Q of the power FET. A ground plane under this circuit is
also recommended.
In applications where it is difficult to place the driver very
close to the power FET (which may result with excessive
parasitic inductance), it then may be necessary to add an
external gate resistor to dampen the inductive ring. If this
resistor must be too large in value to be effective, then as an
alternative, Schottky diodes can be added to clamp the ring
voltage to V+ or GND.
Where high supply voltage operation is required (15V to
18V), input signals with a minimum of 3.3V input drive is
suggested and a minimum rise/fall time of 100ns. This is
recommended to minimize the internal bias current power
dissipation.
Excessive power dissipation in the driver can result when
driving highly capacitive FET gates at high frequencies.
These gate power losses are defined by Equation 1:
where:
P = Power
Q
c
= Charge of the Power FET at V
gs
V
gs
= Gate drive voltage (V+)
f
SW
= switching Frequency
Adding a gate resistor to the output of the driver will transfer
some of the driver dissipation to the resistor. Another
possible solution is to lower the gate driver voltage which
also lowers Q
c
.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask
.
Reliability reports are also available from our website at www.intersil.com/support
FIGURE 14. RECOMMENDED LAYOUT METHODS
GND
V+
C
q
LOOP AS
SHORT AS
POSSIBLE
C
q
SHOULD BE AS CLOSE AS
POSSIBLE TO THE V+ AND
GND PINS
FIGURE 15. SUGGESTED CONFIGURATION FOR DRIVING
INDUCTIVE LOADS
GND
V+
C
q
PARASITIC LEAD
INDUCTANCE
P2Q
C
V
gs
f
SW
=
(EQ. 1)
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE REVISION CHANGE
October 16, 2015 FN6798.2 Updated Ordering Information Table on page 2.
Added Revision History and About Intersil sections.
Updated POD MDP0027 to M8.15E.
ISL89410, ISL89411, ISL89412
