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NCP1652DWR2G

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19
DETAILED DEVICE DESCRIPTION
Introduction
The NCP1652 is a highly integrated controller combining
PFC and an isolated step down ac−dc power conversion in
a single stage, resulting in a lower cost and reduced part
count solution. This controller is ideal for notebook
adapters, battery chargers and other off−line applications
with power requirements between 75 W and 150 W with an
output voltage greater than 12 V. The single stage is based
on the flyback converter and it is designed to operate in CCM
or DCM modes.
Power Factor Correction (PFC) Introduction
Power factor correction shapes the input current of
off−line power supplies to maximize the real power
available from the mains. Ideally, the electrical appliance
should present a load that emulates a pure resistor, in which
case the reactive power drawn by the device is zero. Inherent
in this scenario is the freedom from input current harmonics.
The current is a perfect replica of the input voltage (usually
a sine wave) and is exactly in phase with it. In this case the
current drawn from the mains is at a minimum for the real
power required to perform the needed work, and this
minimizes losses and costs associated not only with the
distribution of the power, but also with the generation of the
power and the capital equipment involved in the process.
The freedom from harmonics also minimizes interference
with other devices being powered from the same source.
Another reason to employ PFC in many of today’s power
supplies is to comply with regulatory requirements. Today,
electrical equipment in Europe must comply with the
European Norm EN61000−3−2. This requirement applies to
most electrical appliances with input power of 75 W or
greater, and it specifies the maximum amplitude of
line−frequency harmonics up to and including the 39
th
harmonic. While this requirement is not yet in place in the
US, power supply manufacturers attempting to sell products
worldwide are designing for compliance with this
requirement.
Typical Power Supply with PFC
A typical power supply consists of a boost PFC
preregulator creating an intermediate X400 V bus and an
isolated dc−dc converter producing the desired output
voltage as shown in Figure 51. This architecture has two
power stages.
Figure 51. Typical Two Stage Power Converter
Rectifier
&
Filter
PFC
Preregulator
DC−DC
Converter
with isolator
AC
Input
V
out
A two stage architecture allows optimization of each
individual power stage. It is commonly used because of
designer familiarity and a vast range of available
components. But, because it processes the power twice, the
search is always on for a more compact and power efficient
solution.
The NCP1652 controller offers the convenience of
shrinking the front−end converter (PFC preregulator) and
the dc−dc converter into a single power processing stage as
shown in Figure 52.
Figure 52. Single Stage Power Converter
Rectifier
&
Filter
NCP1652 Based
Single−Stage
Flyback Converter
AC
Input
V
out
This approach significantly reduces the component count.
The NCP1652 based solution requires only one each of
MOSFET, magnetic element, output rectifier (low voltage)
and output capacitor (low voltage). In contrast, the 2−stage
solution requires two or more of the above−listed
components. Elimination of certain high−voltage
components (e.g. high voltage capacitor and high voltage
PFC diode) has significant impact on the system design. The
resultant cost savings and reliability improvement are often
worth the effort of designing a new converter.
Single PFC Stage
While the single stage offers certain benefits, it is
important to recognize that it is not a recommended solution
for all requirements. The following three limitations apply
to the single stage approach:
• The output voltage ripple will have a 2x line frequency
component (120 Hz for North American applications)
that can not be eliminated easily. The cause of this
ripple is the elimination of the energy storage element
that is typically the boost output capacitor in the
2−stage solution. The only way to reduce the ripple is to
increase the output filter capacitance. The required
value of capacitance is inversely proportional to the
output voltage – hence this approach is not
recommended for low voltage outputs such as 3.3 V or
5 V. However, if there is a follow−on dc−dc converter
stage or a battery after the single stage converter, the
low frequency ripple should not cause any concerns.
• The hold−up time will not be as good as the 2−stage
approach – again due to the lack of an intermediate
energy storage element.
• In a single stage converter, one FET processes all the
power – that is both a benefit and a limitation as the
stress on that main MOSFET is relatively higher.
Similarly, the magnetic component (flyback
transformer/inductor) can not be optimized as well as in
NCP1652, NCP1652A
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the 2−stage solution. As a result, potentially higher
leakage inductance induces higher voltage spikes (like
the one shown in Figure 53) on the MOSFET drain.
This may require a MOSFET with a higher voltage
rating compared to similar dc−input flyback
applications.
Figure 53. Typical Drain Voltage Waveform of a
Flyback Main Switch
There are a few methods to clamp the voltage spike on the
main switch, a resistor−capacitor−diode (RCD) clamp, a
transient voltage suppressor (TVS) or an active clamp using
a MOSFET and capacitor can be used as shown in
Figures 54 to 56.
R
RCD
Clamp
V
out
Figure 54. RCD Clamp
V
in
C
D
TVS
TVS
Clamp
V
out
Figure 55. TVS Clamp
V
in
Active
Clamp
V
out
Figure 56. Active Clamp
V
in
The first two methods result in dissipation of the leakage
energy in the clamping circuits – the dissipation is
proportional to LI
2
where L is the leakage inductance of the
transformer and I is the peak of the switch current at
turn−off. An RDC snubber is simple and has the lowest cost,
but constantly dissipates power. A TVS provides good
voltage clamping at a slightly higher cost and dissipates
power only when the drain voltage exceeds the voltage
rating of the TVS.
The active clamp circuit provides an intriguing alternative
to the other methods. It requires addition of a MOSFET and
a high voltage capacitor as part of the active clamp circuit,
thus adding complexity, but it results in a complete reuse of
the leakage inductance energy. As a result, the transformer
construction is no longer critical and one can use cheaper
cost solution. Also, the active clamp circuit reduces the
voltage stress on the primary switch and that can lead to
usage of lower cost or lower on resistance (R
DS(on)
)
MOSFET. Finally, the turn−on switching losses are
eliminated because the active clamp circuit allows the
discharge of the MOSFET C
OSS
capacitance prior to the
turn−on. The energy stored in the leakage inductance is
utilized for this transition.
In many applications, the added complexity of the active
clamp circuit may not be justified. However, the OUTB of
the NCP1652 is also usable for another purpose,
synchronous rectification control. Synchronous
rectification for flyback converters is an emerging
requirement for flyback converters. The OUTB signal from
NCP1652 is ideal for interfacing with a secondary side
synchronous rectifier controller such as NCP4303 as shown
in Figure 57. As shown in Figure 57, using the OUTB
(coupled through pulse transformer or Y−capacitor) as a
trigger for the NCP4303 allows guaranteed turn−off of the
secondary side synchronous MOSFET prior to turn−on of
the primary switch. In any CCM flyback converter, this is a
critical requirement to prevent cross−conduction and
NCP1652 and NCP4303 combination is the first such
chipset that guarantees the operation without
cross−conduction.
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NCP4303
TRIG
NCP1652
OUTB
OUTA
DRV
Figure 57. NCP1652 and NCP4302 based single stage PFC with synchronous rectification.
V
IN
V
OUT
The NCP1652 incorporates a secondary driver, OUTB,
with adjustable non overlap delay for controlling a
synchronous rectifier switch in the secondary side, an active
clamp switch in the primary or both. In addition, the
controller features a proprietary Soft−Skip™ to reduce
acoustic noise at light loads. Other features found in the
NCP1652 include a high voltage startup circuit, voltage
feedforward, brown out detector, internal overload timer,
latch input and a high accuracy multiplier.
NCP1652 PFC Loop
The NCP1652 incorporates a modified version of average
current mode control used for achieving the unity power
factor. The PFC section includes a variable reference
generator, a low frequency voltage regulation error
amplifier (AC error AMP), ramp compensation (Ramp
Comp) and current shaping network. These blocks are
shown in the lower portion of the bock diagram (Figure 51).
The inputs to the reference generator include feedback
signal (FB), scaled AC input signal (AC_IN) and
feedforward input (V
FF
). The output of the reference
generator is a rectified version of the input sine−wave scaled
by the FB and V
FF
values. The reference amplitude is
proportional to the FB and inversely proportional to the
square of the V
FF
. This, for higher load levels and/or lower
input voltage, the signal would be higher.
The function of the AC error amp is to force the average
current output of the current sense amplifier to match the
reference generator output. The output of the AC error
amplifier is compensated to prevent response to fast events.
This output (V
error
) is fed into the PWM comparator through
a reference buffer. The PWM comparator sums the V
error
and
the instantaneous current and compares it to a 4.0 V
threshold to provide the desired duty cycle control. Ramp
compensation is also added to the input signal to allow CCM
operation above 50% duty cycle.
High Voltage Startup Circuit
The NCP1652 internal high voltage startup circuit
eliminates the need for external startup components and
provides a faster startup time compared to an external
startup resistor. The startup circuit consists of a constant
current source that supplies current from the HV pin to the
supply capacitor on the V
CC
pin (C
CC
). The startup current
(I
start
) is typically 5.5 mA.
The OUTA and OUTB drivers are enabled and the startup
current source is disabled once the V
CC
voltage reaches
V
CC(on)
, typically 15.3 V. The controller is then biased by
the V
CC
capacitor. The drivers are disabled if V
CC
decays to
its minimum operating threshold (V
CC(off)
) typically 10.3 V.
Upon reaching V
CC(off)
the gate drivers are disabled. The
V
CC
capacitor should be sized such V
CC
is kept above
V
CC(off)
while the auxiliary voltage is building up.
Otherwise, the system will not start.
The controller operates in double hiccup mode while in
overload or V
CC(off)
. A double hiccup fault disables the
drivers, sets the controller in a low current mode and allows
V
CC
to discharge to V
CC(off)
. This cycle is repeated twice to
minimize power dissipation in external components during
a fault event. Figure 58 shows double hiccup mode
operation. A soft−start sequence is initiated the second time
V
CC
reaches V
CC(on)
. If the controller is latched upon
reaching V
CC(on)
, the controller stays in hiccup mode.
During this mode, V
CC
never drops below V
CC(reset)
, the
controller logic reset level. This prevents latched faults to be
cleared unless power to the controller is completely
removed (i.e. unplugging the supply from the AC line).
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NCP1652DWR2G

Mfr. #:
Buy NCP1652DWR2G
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC ANA PFC CONTROLLER
Lifecycle:
New from this manufacturer.
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