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NCP1652DWR2G

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28
converter. There is no error in the output signal due to the
series rectifier as shown in Figure 67.
The scaled version of the full wave rectified input ac wave
is applied to the AC_IN pin by means of a resistive voltage
divider. The multiplier ramp is generated by comparing the
scaled line voltage to the oscillator ramp with the AC_IN
Comparator. The current signal from the V-I converter is
factored by the AC_IN comparator output. The resulting
signal is filtered by the low pass R-C filter on the CM pin.
The low pass filter removes the high frequency content. The
gain of the multiplier is determined by the V-I converter, the
resistor on the CM pin, and the peak and valley voltages of
the oscillator sawtooth ramp.
AC IN
−
+
Multiplier
V−to−I
FB
CM
Square
Divide
AC_REF
Oscillator
Figure 67. Reference Generator
V
AC_REF
+ k @
V
FB
@ V
AC_IN
V
FF
2
V
FF
2
V
FF
The third input to the reference generator is the V
FF
signal.
The V
FF
signal is a dc voltage proportional to the ac line
voltage. A resistive voltage divider attenuates the full wave
rectified line voltage between 0.7 and 5.0 V. The full wave
rectified line is then averaged with a capacitor. The ac
average voltage must be constant over each half cycle of the
line. Line voltage ripple (120 Hz or 100 Hz) ripple on the
V
FF
signal adds ripple to the output of the multiplier. This
will distort the ac reference signal and reduce the power
factor and increase the line current distortion. Excessive
filtering delays the feedforward signal reducing the line
transient response. A good starting point is to set the filter
time constant to one cycle of the line voltage. The user can
then optimize the filter for line transient response versus
power factor. The average voltage on the V
FF
pin is:
V
FF
+
2
p
Vac 2a
Ǹ
(eq. 7)
Where, a is the voltage divider ratio, normally 0.01.
V
AC_REF
+
V
FB
@ V
AC_IN
V
FF
2
@ k
(eq. 8)
The multiplier transfer function is given by Equation 8.
The output of the multiplier is the AC_REF. It connects to
the AC Error Amplifier.
where, k is the reference generator gain, typically 0.55. The
output of the reference generator is clamped at 4.5 V to limit
the maximum output power.
Feedforward maintains a constant input power
independent of the line voltage. That is, for a given FB
voltage, if the line voltage doubles (AC_IN), the
feedforward term quadruples and reduces the output of the
error amplifier in half to maintain the same input power.
AC Error Amplifier Compensation
A pole-zero pair is created by placing a series combination
of R
COMP
and C
COMP
at the output of the AC error amplifier
(EA). The value of the compensation components is
NCP1652, NCP1652A
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29
dependent of the average input current and the instantaneous
switch current. The gain of the average input current or slow
loop is given by Equation 9.
A
LF
+
ǒ
R
IAVG
4k
Ǔ
@
ǒ
gm @ R
AC_COMP
Ǔ
@
(
2.286
)
(eq. 9)
The low frequency gain is the product of the current sense
averaging circuit, the transconductance amplifier and the
gain of the AC error amplifier.
A current proportional to the instantaneous current is
generated using a 4 kW resistor in the current sense amplifier
input. This proportional current is applied to a 21.33 kW at
the PWM comparator input to generate a current sense
voltage signal. The high frequency or fast loop gain, A
HF
, is
calculated using Equation 10.
A
HF
+
21.33k
4k
+ 5.333
(eq. 10)
Equation 11 shows system stability requirements. That is,
the low frequency gain has to be less than one half of the high
frequency gain.
ǒ
R
IAVG
4k
Ǔ
@
ǒ
gm @ R
AC_COMP
Ǔ
@ (2.286) t
5.333
2
(eq. 11)
Equation 12 is obtained by re-arranging Equation 11 for
R
AC_COMP
. This equation provides the maximum value for
R
AC_COMP
.
R
AC_COMP
t
4666
R
IAVG
@ gm
(eq. 12)
The control loop zero, f
Z
, is calculated using Equation 13.
The control loop zero should be set at approximately at
1/10
th
of the oscillator frequency, f
OSC
. The compensation
capacitor is calculated using Equation 14.
f
z
+
1
2p @ C
AC_COMP
@ R
AC_COMP
(eq. 13)
C
AC_COMP
+
1
2p @
f
OSC
10
@ R
AC_COMP
(eq. 14)
Current Sense Resistor
The PFC stage has two control loops. The first loop
controls the average input current and the second loop
controls the instantaneous current across the main switch.
The current sense signal affects both loops. The current
sense signal is fed into the positive input of the error
amplifier to control the average input current. In addition,
the current sense information together with the ramp
compensation and error amplifier signal control the
instantaneous primary peak current.
The primary peak current, I
PK
, is calculated using
Equation 15,
I
PK
+
2
Ǹ
@ P
out
h @ V
in(LL)
@ D
)
V
in(LL)
@ t
on
0.88 @ 2 @ L
P
(eq. 15)
where, V
in(LL)
is the low line ac input voltage, D is the duty
ratio, P
out
is the output power, P
in
is the input power, h is the
efficiency, L
P
is the primary inductance and t
on
is the on
time. Typical efficiency for this topology is around 88%.
The current sense resistor is selected to achieve maximum
signal resolution at the input of the ac reference amplifier.
The maximum voltage input of the ac reference amplifier to
prevent saturation is 4.5 V. This together with the
instantaneous peak current is used to calculate the current
sense resistor, R
CS
, using Equation 16.
R
CS
+ 4.5
4k @
ǒ
V
in(LL)
@ D
Ǔ
R
IAVG
@ P
in
@ 2
Ǹ
(eq. 16)
Ramp Compensation
Subharmonic oscillations are observed in peak
current-mode controllers operating in continuous
conduction mode with a duty ratio greater than 50%.
Injecting a compensation ramp on the current sense signal
eliminates the subharmonic oscillations. The amount of
compensation is system dependent and it is determined by
the inductor falling di/dt.
The NCP1652 has built in ramp compensation to facilitate
system design. The amount of ramp compensation is set by
the user with a resistor, R
RCOMP
, between the Ramp Comp
pin and ground. The Ramp Comp pin buffers the oscillator
ramp generated on the C
T
pin. The current across R
RCOMP
is internally mirrored with a 1:1.2 ratio. The inverted ac error
amplifier and the instantaneous switch current signals are
added to the ramp compensation mirrored current. The
resulting current signal is applied to an internal 21.33 kW
between the PWM Comparator non inverting input and
ground as shown in Figure 64.
The maximum voltage contribution of the ramp
compensation signal to the error signal, V
RCOMP
, is given by
Equation 17.
V
RCOMP
+
(
1.2
)
@
ǒ
V
CT(peak)
Ǔ
@
(
21.33k
)
R
RCOMP
+
102.38k
R
RCOMP
(eq. 17)
where, V
CT(peak)
is the oscillator ramp peak voltage,
typically 4.0 V.
For proper ramp compensation, the ramp signal should
match the falling di/dt (which has been converted to a dv/dt)
of the inductor at 50% duty cycle. Both the falling di/dt and
output voltage need to be reflected by the transformer turns
ratio to the primary side. Equations 18 through 23 assist in
the derivation of equations for R
CS
and R
COMP
.
di
dt
secondary
+
V
out
L
S
+
V
out
L
P
@
ǒ
N
P
N
S
Ǔ
2
(eq. 18)
di
dt
primary
+
di
dt
secondary
@
N
S
N
P
+
V
out
L
P
N
P
N
S
(eq. 19)
NCP1652, NCP1652A
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30
V
RCOMP
+
di
dt
primary
@ T @ R
CS
@ A
HF
(eq. 20)
R
CS
+
N
S
N
P
@
L
P
@ 102.38k
T @ A
HF
@ V
out
@ R
RCOMP
(eq. 21)
At low line and full load, the output of the ac error
amplifier output is nearly saturated in a low state. While the
ac error amplifier output is saturated, I
ACEA
is zero and does
not contribute to the voltage across the internal 21.33 kW
resistor on the PWM comparator non-inverting input. In this
operation mode, the voltage across the 21.33 kW resistor is
determined solely by the ramp compensation and the
instantaneous switch current as given by Equation 22.
V
ref(PWM)
+
ǒ
V
RCOMP
@
t
on
T
Ǔ
) V
INST
(eq. 22)
The voltage reference of the PWM Comparator,
V
REF(PWM)
, is 4 V. For these calculations, 3.8 V is used to
provide some margin. The maximum instantaneous switch
current voltage contribution, V
INST
, is given by
Equation 23.
V
INST
+ I
PK
@ R
CS
@ A
HF
(eq. 23)
Substituting Equation 23 in Equation 22, setting
V
REF(PWM)
at 3.8 V (provides margin) and solving for
R
RCOMP,
Equation 24 is obtained.
R
RCOMP
+
102.38k
ǒ
3.8 * 5.333 @ I
PK
@ R
CS
Ǔ
@
t
on
T
(eq. 24)
Replacing Equation 24 in Equation 21 we obtain:
R
CS
+
3.8
ǒ
N
P
N
S
@
A
HF
@V
out
@t
on
L
P
Ǔ
) 5.333 I
PK
(eq. 25)
PWM Logic
The PWM and logic circuits are comprised of a PWM
comparator, an RS flip-flop (latch) and an OR gate. The
latch is Set dominant which means that if both R and S are
high the S signal will dominate and Q will be high, which
will hold the power switch off.
The NCP1652 uses a pulse width modulation scheme
based on a fixed frequency oscillator. The oscillator
generates a voltage ramp as well as a pulse in sync with the
falling edge of the ramp. The pulse is an input to the PWM
Logic and Driver block. While the oscillator pulse is present,
the latch is reset, and the output drive is in its low state. On
the falling edge of the pulse, the OUTA goes high and the
power switch begins conduction.
The instantaneous inductor current is summed with a
current proportional to the ac error amplifier output voltage.
This complex waveform is compared to the 4 V reference
signal on the PWM comparator inverting input. When the
signal at the non-inverting input to the PWM comparator
exceeds 4 V, the output of the PWM comparator toggles to
a high state which drives the Set input of the latch and turns
the power switch off until the next clock cycle.
Brown−Out
The NCP1652 incorporates a brown−out detection circuit
to prevent the controller operate at low ac line voltages and
reduce stress in power components. A scaled version of the
rectified line voltage is applied to the VFF Pin by means of
a resistor divider. This voltage is used by the brown out
detector.
A brown−out condition exists if the feedforward voltage
is below the brown−out exit threshold, V
BO(high)
, typically
0.45 V. The brown−out detector has 180 mV hysteresis. The
controller is enabled once V
FF
is above 0.63 V and V
CC
reaches V
CC(on)
. OUTB is the last drive pulse. Figure 68
shows the relationship between the brown−out, V
CC
, OUTA
and OUTB signals.
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NCP1652DWR2G

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Buy NCP1652DWR2G
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC ANA PFC CONTROLLER
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