OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7191BRUZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD7191
Rev. A | Page 6 of 20
TIMING CHARACTERISTICS
AV
DD
= 3 V to 5.25 V; DV
DD
= 2.7 V to 5.25 V; AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV
DD
, unless otherwise noted.
Table 2.
Parameter
1, 2
Limit at T
MIN
, T
MAX
(B Version) Unit Conditions/Comments
t
3
100 ns min SCLK high pulse width
t
4
100 ns min SCLK low pulse width
Read Operation
t
1
0 ns min
PDOWN falling edge to DOUT/RDY
active time
60 ns max DV
DD
= 4.75 V to 5.25 V
80 ns max DV
DD
= 2.7 V to 3.6 V
t
2
3
0 ns min SCLK active edge to data valid delay
4
60 ns max DV
DD
= 4.75 V to 5.25 V
80 ns max DV
DD
= 2.7 V to 3.6 V
t
5
5, 6
10 ns min Bus relinquish time after PDOWN inactive edge
80 ns max
t
6
0 ns min SCLK inactive edge to PDOWN inactive edge
t
7
10 ns min
SCLK inactive edge to DOUT/RDY
high
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 3.
3
These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
The SCLK active edge is the falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY
returns high after a read of the ADC. The digital word can be read only once.
I
SINK
(1.6mA WITH DV
DD
= 5V,
100µA WITH DV
DD
= 3V)
I
SOURCE
(200µA WITH DV
DD
= 5V,
100µA WITH DV
DD
= 3V)
1.6V
TO
OUTPUT
PIN
50pF
08163-002
Figure 2. Load Circuit for Timing Characterization
TIMING DIAGRAM
t
1
t
3
t
2
t
7
t
6
t
5
t
4
PDOWN (I)
NOTES
1. I = INPUT, O = OUTPUT
DOUT/RDY (O)
SCLK (I)
08163-003
Figure 3. Read Cycle Timing Diagram
AD7191
Rev. A | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AV
DD
to AGND
−0.3 V to +6.5 V
DV
DD
to DGND
−0.3 V to +6.5 V
AGND to DGND −0.3 V to +0.3 V
Analog Input Voltage to AGND
−0.3 V to AV
DD
+ 0.3 V
Reference Input Voltage to AGND
−0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to DGND
−0.3 V to DV
DD
+ 0.3 V
Digital Output Voltage to DGND
−0.3 V to DV
DD
+ 0.3 V
AIN/Digital Input Current 10 mA
Operating Temperature Range
−40°C to +105°C
Storage Temperature Range
−65°C to +150°C
Maximum Junction Temperature 150°C
TSSOP
θ
JA
Thermal Impedance 128°C/W
θ
JC
Thermal Impedance 42°C/W
Lead Temperature, Soldering
Reflow 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7191
Rev. A | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
12
11
MCLK2
SCLK
PDOWN
PGA1
PGA2
CLKSEL
MCLK1
CHAN
TEMP
AIN2
AIN1
NC
20
21
22
23
24
19
18
17
16
15
14
13
DOUT/RDY
ODR1
DV
DD
AGND
DGND
AV
DD
BPDSW
REFIN(–)
AIN3
AIN4
REFIN(+)
ODR2
AD7191
TOP VIEW
(Not to Scale)
08163-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 MCLK1
When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2. Alternatively, the MCLK1 pin can be driven with a CMOS-compatible clock and MCLK2
left unconnected.
2 MCLK2
When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2.
3 SCLK
Serial Clock Input. This serial clock input is for controlling data transfers from the ADC. The SCLK has a
Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can
be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a non-
continuous clock with the information transmitted to or from the ADC in smaller batches of data.
4 PDOWN Power-Down Pin, Digital Input. The PDOWN pin functions as a power-down pin and a reset pin. When
PDOWN is taken high, the AD7191 is powered down and the DOUT/RDY
pin is tristated. The circuitry and
serial interface are also reset. This resets the logic, the digital filter, and the analog modulator. PDOWN
must be held high for 100 ns minimum to initiate the reset function.
5 CLKSEL
Clock Select, Digital Input Pin. This pin selects the clock source to be used by the AD7191. When CLKSEL is
tied low, the external clock/crystal is used as the clock source. When CLKSEL is tied high, the internal
4.92 MHz clock is used as the clock source to the AD7191.
6 PGA2 Gain Select, Digital Input Pin. This pin is used in conjunction with PGA1 to set the gain. See Table 7.
7 PGA1 Gain Select, Digital Input Pin. This pin is used in conjunction with PGA2 to set the gain. See Table 7.
8 CHAN Channel Select, Digital Input Pin. This pin is used to select the channel.
When CHAN is tied low, channel AIN1/AIN2 is selected.
When CHAN is tied high, channel AIN3/AIN4 is selected.
9 TEMP
Temperature Sensor Select, Digital Input Pin. The internal temperature sensor is selected when TEMP is
tied high. When TEMP is tied low, the analog input channel AIN1/AIN2 or AIN3/AIN4 is the selected
channel (as determined by the CHAN pin).
10 NC No Connect. This pin should be tied to AGND.
11 AIN1
Analog Input. AIN1 is the positive input of the fully differential input pair AIN1/AIN2.
12 AIN2 Analog Input. AIN2 is the negative input of the fully differential input pair AIN1/AIN2.
13 AIN3 Analog Input. AIN3 is the positive input of the fully differential input pair AIN3/AIN4.
14 AIN4
Analog Input. AIN
4 is the negative input of the fully differential input pair AIN3/AIN4.
15 REFIN(+)
Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+)
can lie anywhere between AV
DD
and AGND + 1 V. The nominal reference voltage, (REFIN(+) − REFIN(−)), is
AV
DD
, but the part functions with a reference from 1 V to AV
DD
.
16 REFIN(−) Negative Reference Input. This reference input can lie anywhere between AGND and AV
DD
− 1 V.
17 BPDSW
Bridge Power-Down Switch to AGND. When PDOWN is low, the bridge power-down switch is closed.
When PDOWN is high, the bridge power-down switch is opened.
18 AGND Analog Ground Reference Point.
19 DGND Digital Ground Reference Point.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7191BRUZ

Mfr. #:
Buy AD7191BRUZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2CH Ultra Low Noise 24Bit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet