MAX2741ETI+T Datasheet MAX2741ETI+, MAX2741ETI+T | P4-P6

MAX2741

Integrated L1-Band GPS Receiver

4 _______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 LNA Supply Connection. External RF bypass capacitor to ground required.

2, 20, 22, 23

N.C. Reserved. Make no connections to this pin.

3 RFIN

LNA Input. Connect to GPS antenna through a bandpass filter. This input requires an external

matching network to match to 50Ω. AC-couple to this pin.

2 VCO Supply Connection. External RF bypass capacitor to ground required.

3 CML Supply Connection. External RF bypass capacitor to ground required.

4 Digital Logic and PLL Supply Connection. External RF bypass capacitor to digital ground required.

7 GND Ground. Connect to PC board digital ground plane.

8 FILT

PLL Loop Filter Connection. This is the output of the phase detector’s charge pump. Use the

recommended filter on EV kit for optimal phase noise and lock time.

9 SCLK SPI Clock Input (CMOS)

10 CS SPI Chip-Select Input (CMOS, Active Low)

11 SDI SPI Data Input (CMOS)

12 SHDN

Full IC Power-Down. This shutdown pin disables the on-chip oscillator and the rest of the IC. To keep

the oscillator running, use the software shutdown (SYNTH:D8); (CMOS, active high).

13 XTAL Crystal Oscillator Feedback Capacitor Connection

14 REFCLK Reference Clock Input for PLL. Drive with 1.2V

P-P

when using TCXO module.

15 GPSCLK

GPS Clock Output to Baseband. This is the clock used by the ADC to sample the GPS data (CMOS).

16 GPSIF2 Sampled IF Output, Bit 2 (CMOS). See Table 5.

17 GPSIF1 Sampled IF Output, Bit 1 (CMOS). See Table 5.

18 GPSIF0 Sampled IF Output, Bit 0 (CMOS). See Table 5.

19 V

5IF Supply Connection. External RF bypass capacitor to ground required.

21 SDO SPI Data Output (CMOS)

24 IFIN-

1st IF Input (Inverting). Connect this 2.5kΩ differentially terminated input to the 1st IF filter’s (-) output.

25 IFIN+

1st IF Input (Noninverting). Connect this 2.5kΩ differentially terminated input to the 1st IF filter’s (+)

output.

26 IFOUT- 1st IF Output (Inverting). Connect this 2.4kΩ differential output to the 1st IF filter’s (-) input.

27 IFOUT+ 1st IF Output (Noninverting). Connect this 2.4kΩ differential output to the 1st IF filter’s (+) input.

28 V

6 RF Image-Reject Mixer Supply. External RF bypass capacitor to ground required.

Exposed

GND

RF Ground. Ultra-low inductance connection to ground. Place several vias to PC board ground plane.

MAX2741

Integrated L1-Band GPS Receiver

_______________________________________________________________________________________ 5

Detailed Description

The MAX2741 GPS offers a high-performance super-

heterodyne receiver solution for low-power mobile

devices, with the benefit of using the system’s existing

clock reference. This receiver is ideal for integration into

mobile phone handsets using common reference fre-

quencies such as 10.0, 13.0, 14.4, 19.2, 20.0, and

26.0MHz. The only external components required are the

GPS RF filter, an IF filter (typically designed from inexpen-

sive discretes), a three-component PLL loop filter, and a

few other resistors and capacitors. The MAX2741 inte-

grates the reference oscillator core, the VCO and its tank,

the synthesizer, a 1- to 3-bit ADC, and all signal path

blocks except for the 1st IF filter. The typical application

area for the receiver is less than 2cm

RF/1st Conversion Stage (Front-End)

The MAX2741 RF front-end LNA and mixer are the most

important in the signal path. This stage sets the noise

figure for the receiver, defining the sensitivity, and mixes

the 1575.42MHz L1-band GPS signal down to a 1st IF of

37.38MHz. The LNA itself has an NF of approximately

1.5dB; the cascaded NF of the front-end (including the

mixer) is approximately 4.7dB, and the cascaded gain

is typically 21dB.

The image-reject mixer is set up for a high-side injected

RFLO (1612.80MHz), and offers typically better than 30dB

rejection of the image noise (1650.18MHz). The -30dBm

input 3rd-order intercept (IIP3) of the RF strip, in conjunc-

tion with the GPS IF filter, provides excellent out-of-band

interferer immunity.

The 1st IF outputs (IFOUT±) are internally biased to

approximately 2V, and have a differential source

impedance of approximately 2.5kΩ. The IF filter can be

implemented as a discrete L/C filter, or as a monolithic

SAW or ceramic if one is available.

IF/2nd Conversion Stage

The 2nd conversion stage consists of an active mixer, a

variable-gain amplifier (VGA), and a tunable lowpass

filter. The IF mixer is configured for low-side LO injec-

tion for a 2nd IF of 3.78MHz. Total gain in this stage is

62dB, and the VGA offers 51dB of gain adjustment. The

VGA is typically controlled by the baseband IC through

the SPI interface to optimize the signal swing for digiti-

zation by the ADC.

The on-chip lowpass filter has an adjustable cutoff fre-

quency, programmable from 2.9MHz to 7.7MHz in 16

steps. This LPF further reduces out-of-band noise and

band-limits the signal to the ADC, ensuring that the

sampling process does not generate alias components.

DC offset compensation at the ADC input is performed by

an on-chip 4-bit DAC. This compensates for any DC error

introduced by transistor mismatch in the differential stage

driving the ADC input, allowing the downconverted GPS

signal’s DC level to be centered within the threshold volt-

ages of the ADC.

ADC

The on-chip ADC samples the down-converted GPS

signal at the 2nd IF (3.78MHz). Sampled output is pro-

vided in either 2-bit (1-bit magnitude, 1-bit sign) or 3-bit

(2-bit magnitude, 1-bit sign) formats, as determined by

the ADC mode configuration bit (CONFIG1:D15); see

Table 5 for details. The ADC sample clock (system GPS

clock) is derived either directly from the reference clock

(SYNTH:D9 = 1), or from an RFLO divide-by-96 block to

provide a 16.8MHz sample clock (SYNTH:D9 = 0). The

clock is available to the baseband processor at

GPSCLK (pin 15). The sampled ADC data bits are

available on pins 16, 17, and 18 (GPSIF2, GPSIF1, and

GPSIF0). The functionality of the pins is different in

each mode (2-bit vs. 3-bit)—see Table 5 in determining

the interface connection for the application circuit.

Synthesizer

The MAX2741 integrates an integer-N synthesizer; all

blocks except the loop filter are on-chip. The reference

can be either a crystal (driven by the internal oscillator),

or a TCXO module. The oscillator provides a 5pF load

to the crystal. A TCXO module should provide a swing

in the 0.6V

P-P

to 2.2V

P-P

range.

The reference divider (/R) is programmable (SYNTH:

D7–D0), and can accommodate reference frequencies

up to 26MHz. The reference divider needs to be set so

the comparison frequency (f

COMP

) at the frequency/

phase detector is 200kHz. The VCO runs at twice the fre-

quency of the RFLO; the RFLO is therefore generated

from the VCO using a quadrature divide-by-2 block. The

RF LO is f

COMP

x 8064 (typically 1612.80MHz), and the

1st IF LO is f

COMP

x 168 (typically 33.6MHz); the RF and

IF LO division ratios are not adjustable. This configuration

allows for the use of reference frequencies common to

GSM, CDMA, TDMA, TD-SCDMA, and UMTS handsets:

9.6MHz (R = 48), 13.0MHz (R = 65), 14.4MHz (R = 72),

19.2MHz (R = 96), 26.0MHz (R = 130), etc.

MAX2741

Integrated L1-Band GPS Receiver

6 _______________________________________________________________________________________

The VCO offers a bank of tuning capacitors that can be

latched in/out to adjust the center frequency. Because

the system does not require any RF LO frequency

change (i.e., changing channels), the VCO varactor tun-

ing gain is very low by design, which means the tuning

range of the VCO is narrow. The coarse-tune capacitors

in the tank circuit allow the system to adjust the VCO

center frequency as needed to guarantee that the syn-

thesizer can lock. In practice, process and temperature

effects on VCO centering are negligible, and a coarse-

tune setting of 110 (CONFIG:D7 to D5) will center the

VCO tuning range correctly in virtually all cases. To aid in

bench and prototype testing, the PFD offers out-of-lock-

high and out-of-lock-low indicators, available in the SPI

STATUS register (STATUS:D9 to D8). Use these flags to

determine if the VCO tuning range needs to be adjusted

higher or lower in the case where the PLL cannot lock.

The PLL filter is the only external block of the synthesizer.

The typical filter is a classic C-R-C two-pole shunt network

on the tune line. Low phase noise is preferred at the

expense of longer PLL settling times, so a low 10kHz to

20kHz loop bandwidth is used. The recommended PLL

10kHz filter implementation, with charge pump set to

200µA (CONFIG1:D10 = 1), is shown in Figure 1.

The system/GPS clock is derived either directly from

the reference oscillator, or synthesized from the RFLO

(see the ADC section). This clock is used as the sam-

pling clock for the on-chip ADC, and is seen at pin 15,

GPSCLK.

SPI Bus, Address and Bit Assignments

An SPI-compatible serial interface is used to program the

MAX2741 for configuring the different operating modes.

In addition, data can be read out of the MAX2741 for sta-

tus and diagnostic use. The serial interface is controlled

by four signals: SCLK (serial clock), CS (chip-select), SDI

(data input), and SDO (data output).

The control of the PLL, AGC, test, offset management,

and block selection is performed through the SPI bus

from the baseband controller. A 20-bit word, with the MSB

(D15) being sent first, is clocked into a serial shift register

when the chip-select signal is asserted low.

The SPI bus has four control lines: serial clock (SCLK),

chip-select (CS), data in (SDI), and data out (SDO).

Enable SDO functionality by setting the digital test bus

bits: CONFIG1:D9 to D8 = 01. The timing of the inter-

face signals is shown in Figure 2 and Table 1 along

with typical values for setup and hold time require-

ments.

For best performance, the SPI bus should be configured

during the startup initialization and then left with the opti-

mum values in the registers. Any changes to the ADC

and VGA bits during GPS signal processing may cause

glitches and corrupt the analog signal path. Reading

from the SPI bus does not interrupt GPS operation.

GND

FILT

SCLK

MAX2741

22nF

36kΩ

100pF

Figure 1. Recommended 3rd-Order PLL Filter

LSB MSB

SCLK

SDI

SETUPD

HDATA

PERIOD

END

SETUPSS

Figure 2. SPI Timing Diagram

Table 1. SPI Timing Requirements

SYMBOL

PARAMETER

TYP

VALUE

UNITS

SETUPD

Data to SCLK setup 20 ns

PERIOD

SCLK period 100 ns

HDATA

Data hold to SCLK 20 ns

SETUPSS

CS to SCLK disable 20 ns

END

Falling SCLK to CS inactive

20 ns

P1-P3 P4-P6 P7-P9 P10-P12

MAX2741ETI+T

Mfr. #:

Buy MAX2741ETI+T

Manufacturer:

Maxim Integrated

Description:

RF RECEIVER 1575.42MHZ 28TQFN

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX2741ETI+T

MAX2741ETI+T

Products related to this Datasheet