MAX2741ETI+T

MAX2741
Integrated L1-Band GPS Receiver
_______________________________________________________________________________________ 7
Table 2. Register Address and Data Bit Assigments (Write)
DATA ADDRESS
REGISTER
NAME
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1
A0
SYNTH
Reserved
LPF Autotune
Initiate
LPF Tuning
Word (MSB)
LPF Tuning
Word
LPF Tuning
Word
LPF Tuning
Word (LSB)
XTAL Clock
Select
Standby
PLL Ref Div
Ratio (MSB)
PLL Ref Div
Ratio
PLL Ref Div
Ratio
PLL Ref Div
Ratio
PLL Ref Div
Ratio
PLL Ref Div
Ratio
PLL Ref Div
Ratio
PLL Ref Div
Ratio (LSB)
010
0
CONFIG 1
ADC Mode
ADC Offset Control
(LSB)
ADC Offset Control
ADC Offset Control
(MSB)
ADC Offset Control
(SIGN)
Double Charge-
Pump Current
Digital Test Bus
Mode Select (MSB)
Digital Test Bus
Mode Select (LSB)
VCO Coarse Tuning
Range (MSB)
VCO Coarse Tuning
Range
VCO Coarse Tuning
Range (LSB)
AGC Gain (MSB)
AGC Gain
AGC Gain
AGC Gain
AGC Gain (LSB)
010
1
CONFIG 2
Reset CMOS
Drive VCO Low
Drive VCO High
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Analog Test
Mode Select
Analog Test
Mode Select
Analog Test
Mode Select
Analog Test
Mode Select
Analog Test
Mode Select
011
0
Table 3. Register Address and Data Bit Assigments (Read)
DATA ADDRESS
REGISTER
NAME
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1
A0
STATUS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Out-of-Lock
(High)
Out-of-Lock
(Low)
XTAL Clock
Selected
Parity
Reserved
LPF Auto-
calibrate End
LPF Autotune
(MSB)
LPF Autotune
LPF Autotune
LPF Autotune
(LSB)
011
1
MAX2741
Integrated L1-Band GPS Receiver
8 _______________________________________________________________________________________
Detailed Register Definitions
Table 4. Detailed Register Definition for Write Address 0100: SYNTH
DATA BIT
DEFAULT
DESCRIPTION
D15 1 Reserved
D14 1 LPF Autotune Initiate: I = Initiate autotune, 0 = Manual tuning.
D13–D10
0100 LPF Tuning Word: 0000 ~ 7.7MHz, 1111 ~ 2.9MHz.
D9 1 XTAL Clock Select: 1 = External reference, 0 = Synthesized 16.8MHz.
D8 0 Standby: 0 = Normal operating mode, 1 = Standby (oscillator remains active), but only if D9 = 1.
D7–D0
01100000
Reference Division Ratio. Default 19.2MHz external reference (R = 96dec). R = f
REF
/ 200kHz.
Table 5. Detailed Register Definition for Write Address 0101: CONFIG 1
DATA BIT
DEFAULT
DESCRIPTION
D15 1
ADC Mode. Select 1 for 1-bit magnitude and sign, select 0 for 2-bit magnitude and sign.
1: GPSIF2 = sign, GPSIF1 = magnitude, GPSIF0 = X
0: GPSIF2 = MSB magnitude, GPSIF1 = LSB magnitude, GPSIF0 = sign
D14–D11
0000 ADC Offset Control (approx 4mV/step): D14 = LSB, D12 = MSB, D11 = sign.
D10 0 Double Charge-Pump Current: 0 = 100µA, 1 = 200µA.
D9 to D8
00 Digital Test Bus Mode Select. See Table 9 for test-mode descriptions.
D7 to D5
001 VCO Coarse Tuning Range. 000 = Lowest frequency, 111 = Highest frequency.
D4–D0 11111
AGC Gain. Digital control of the AGC amplifier in the 2nd IF section. 00000 => min gain, 11111 =>
max gain (linear gain ~2.5dB per unit SPI word).
Table 6. Detailed Register Definition for Write Address 0110: CONFIG 2
DATA BIT
DEFAULT
DESCRIPTION
D15 1 Reset CMOS: 0 = Hold CMOS dividers in reset and PFD is tri-stated, 1 = Inactive.
D14 1
Drive VCO Low: 0 = Active, forces VCO to lowest frequency.
N.B. do not activate both D14 and D13 at the same time.
D13 1
Drive VCO High: <forces LCP low FET on, driving V
TUNE
low, forcing VCO to highest extreme> 0 =
Active, forces VCO to highest frequency. N.B. do not activate both D14 and D13 at the same time.
D12–D7 100000 Reserved
D6 to D5
11 Must be programmed to 11
D4–D0 11111 Analog Test Mode Select: Reserved
MAX2741
Integrated L1-Band GPS Receiver
_______________________________________________________________________________________ 9
Applications Information
Fundamentally, the only application areas that require
careful consideration are the LNA input match and the
1st IF filter. Of course, proper supply bypassing,
grounding, and layout is required for reliable perfor-
mance from any RF circuit.
LNA Input Matching
Input matching is critical for optimum noise figure and
system sensitivity. Optimum source impedance (as seen
from the LNA input) for lowest noise figure is 29+ j47.
Remember that optimum noise match and optimum gain
match (return loss) do not occur simultaneously, so a
good application circuit will sacrifice gain slightly in favor
of reduced noise figure. Gain and noise circles are pro-
vided in Figure 3; S11 tabular data is provided in Table 8.
1st IF Interface and Filtering
The typical application uses a 37.38MHz 1st IF, and
employs an IF filter. The order of the filter should be tai-
lored to suit the application—stand-alone GPS
receivers will not require the channel-selection and
stopband attenuation of GPS receivers that are inte-
grated into other wireless handsets. Be sure that the fil-
ter topology provides DC-blocking for the IF I/O ports.
Table 7. Detailed Register Definition for Read Address 0111: STATUS
DATA BIT
DEFAULT
DESCRIPTION
D15–D10
XXXXXX Reserved
D9 X
Out-of-Lock (High Frequency): 1 = PLL is out of lock, VCO free-running at its highest frequency,
0 = Locked.
D8 X
Out-of-Lock (Low Frequency): 1 = PLL is out of lock, VCO free-running at its lowest frequency,
0 = Locked high.
D7 1 XTAL Clock Selected: 1 = Synthesized 16.8MHz reference, 0 = External clock.
D6 X Parity: 1 = Even, 0 = Odd.
D5 X Reserved
D4 X LPF Autotune End: 0 = Autotune run ended; 1 = Calibrating or manual tuning.
D3–D0 XXXX LPF Autotune: 0000 ~ 7.7MHz; 1111 = 2.9MHz.
Table 8. MAX2741 S11
G = Gmax - 1dB
NF = NFmin + 0.2dB
Figure 3. Gain and Noise Circles for MAX2741 LNA Input
FREQ (MHz) S11 (MAG) S11 (°)
1100 0.874 -50.9
1200 0.867 -56.1
1300 0.859 -61.5
1400 0.842 -66.9
1500 0.821 -72.3
1550 0.809 -74.9
1560 0.806 -75.4
1570 0.804 -75.9
1575 0.803 -76.2
1580 0.801 -76.4
1590 0.799 -77.0
1600 0.796 -77.5
1650 0.783 -80.0
1700 0.768 -82.5
1800 0.739 -87.4
1900 0.708 -92.3
2000 0.677 -96.8

MAX2741ETI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
RF RECEIVER 1575.42MHZ 28TQFN
Lifecycle:
New from this manufacturer.
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