LTC2952IF#TRPBF Datasheet LTC2952IF#PBF, LTC2952CUF#TRPBF, LTC2952CF#TRPBF | P16-P18

LTC2952

2952fb

APPLICATIONS INFORMATION

pin of a DC/DC converter. The PB input achieves PowerPath

control by toggling this EN pin.

Note that in this application both of the ideal diodes are

enabled all the time, therefore either Q1 or Q2 can be

replaced by Schottky diodes as long as the voltage drop

across the Schottky diodes and their reverse leakage cur-

rents are acceptable.

Configuration B:

Pushbutton Controller with Preferential WALL Adapter

Operation and Automatic Switchover to Battery

In this configuration (Figure 4) the M1 pin is connected

to ground and the M2 pin is used as a monitor on the

wall adapter input to alter the behavior of the ideal diode

drivers. When the wall adapter voltage is below the trip

threshold, both of the ideal diodes are enabled.

When the wall adapter voltage is above the trip threshold,

the primary ideal diode driver is disabled (shutting off Q1

and Q3) and the secondary ideal diode driver is enabled

(turning on Q2). This means the load current will be sup-

plied from the wall adapter (V2) regardless of the voltage

level at the battery (V1).

If the wall adapter voltage trip threshold is set lower than

the battery input voltage level and the wall adapter input

can go high impedance, the capacitance on V2 needs to

be minimized. This is to ensure proper operation when the

wall adapter goes high impedance and Q1, Q3 is instantly

turned on.

Noting the possible current path through the PFET body

diode, a back-to-back PFET configuration must be used

for Q1, Q3 to make sure that no current will flow from the

battery (V1) to the VS pin even if the wall adapter (V2)

voltage is less than the battery (V1) voltage.

Configuration C:

Pushbutton Control of Ideal Diode Drivers

In this configuration the M2 pin is tied to the M1 pin.

Since the M1 pin has a 3μA internal pull-up current, this

current causes both M1 and M2 to pull high. This allows

the PB pin to have complete control of both the ideal diode

drivers and the EN pin.

The first valid pushbutton input turns on both of the ideal

diode drivers causing the VS pin to be driven to the higher

of either the wall adapter or the battery input – providing

power to the system directly. Conversely, a valid pushbut-

ton off input turns off the ideal diodes after the shutdown

sequence involving an interrupt to the system.

Figure 4. PowerPath Configuration B

LTC2952

DC/DC

SHDN

R10

2952 F04

Q1 Q3

**WALL ADAPTER

TO SYSTEM

*EXTERNAL PULL-UP

REQUIRED

**WALL CAN BE LESS

THAN BATTERY

BATTERY

Figure 5. PowerPath Configuration C

LTC2952

2952 F05

Q1 Q3

WALL ADAPTER

TO SYSTEM

BATTERY

Configuration D:

Battery Backup with Pushbutton PowerPath Controller

In this configuration shown in Figure 6, the M1 pin is left

floating allowing its own 3μA internal pull-up to pull itself

above threshold. With M1 high, the device operates such

that rising and falling edges on the M2 pin are interpreted

as digital on and off commands respectively.

In Figure 6, the M2 pin monitors the wall adapter voltage.

When power is first applied to the wall adapter so that the

voltage at the M2 pin rises above its rising trip threshold

LTC2952

2952fb

APPLICATIONS INFORMATION

(0.515V), both of the ideal diode drivers and the DC/DC

converter are enabled. Thus, power is delivered to the

system.

As soon as the wall adapter voltage falls below its trip

threshold, a shutdown sequence is immediately started. At

the end of the shutdown sequence, the ideal diode drivers

and the DC/DC converter are disabled. Thus, power is cut

off from the load and the system is in shutdown.

Note that once power is delivered to the system, the PB pin

can be used to turn off the power. If PB is used to turn off

the power in this configuration, there are two methods to

turn the power back on: a valid pushbutton on event at the

PB pin or a recycling of the wall adapter voltage (bringing

the voltage level at the M2 pin down below and then back

up above its threshold – a digital on command).

Also note that in this application, the voltage threshold of

the wall adapter input (being monitored at the M2 pin) is

usually set higher than the battery input voltage. Therefore,

the only time when power is drawn from the battery (V1

pin) to the load is during the shutdown sequence when

the voltage at the wall adapter input (V2 pin) has collapsed

below the battery input voltage level.

Reverse Battery Protection

To protect the LTC2952 from a reverse battery connection,

place a 1k resistor in series with the respective supply pin

intended for battery connection (V1 and/or V2) and remove

any capacitance on the protected pin. Figure 7 shows a

configuration with a reverse battery protection on the V1

pin. This resistor will limit the amount of current that flows

out of the V1 pin when a battery is connected in reverse

and protect the part.

Note however, this reverse battery protection resistor

should not be too large in value since the V1 and V2 pins

are also used as the anode sense pins of the ideal diode

drivers. When the ideal diode driver is on, the VS pin

supplies most of the quiescent current of the part (60μA

typ) and the supply pin supplies the remaining quiescent

current (20μA typ). Therefore, the recommended 1k reverse

battery protection resistor amounts to an additional 20mV

(1k • 20μA) drop across the P-channel MOSFET.

In Figure 7, when the battery voltage is larger than the wall

adapter voltage, the battery supplies the load current to

the DC/DC converter. The ideal diode driver regulates G1

to maintain a fixed voltage drop from V1 to VS of 20mV

(typ). Since there is a 20mV drop across the reverse battery

protection resistor (R1) then the regulated voltage drop

from the battery to the VS pin is 40mV (typ).

Figure 6. PowerPath Configuration D

LTC2952

DC/DC

SHDN

R10

2952 F06

WALL ADAPTER

TO SYSTEM

BATTERY

*EXTERNAL PULL-UP

REQUIRED

Figure 7. Reverse Battery Protection on V1

LTC2952

DC/DC

SHDN

2952 F07

WALL ADAPTER

*MINIMIZE CAPACITANCE ON V1

**EXTERNAL PULL-UP REQUIRED

BATTERY

R12

Pushbutton Input and Circuitry

The PB pin is a high impedance input to an accurate com-

parator with a 10μA pull-up to an LDO regulated internal

supply of 4V. The PB input comparator has a 0.775V falling

trip threshold with 25mV hysteresis. Protection circuitry

allows the PB pin to operate over wide range from –6V

to 28V with an ESD HBM rating of ±8kV.

The pushbutton circuitry debounces the input into the PB

pin that sets an internal ON/OFF signal. This signal initiates

a turn ON/OFF power sequence.

LTC2952

2952fb

APPLICATIONS INFORMATION

The timing diagram in Figure 8 shows the PB pin being

debounced and setting an internal ON/OFF signal. Note that

a high at the internal ON/OFF signal indicates that the last

event was a turn-on command and a low at the internal

ON/OFF signal indicates that the last event was a turn-off

command. Here specifically the turn-on command is a

result of a pushbutton on event and the turn-off command

is a result of a pushbutton off event.

Note that a complete pushbutton consists of a push event

and a release event. The push event (falling edge) on and

off debounce durations on the PB pin can be increased

beyond the fixed internal 26ms by placing a capacitor on

the ONT and OFFT pins respectively. The following equa-

tions describe the additional debounce time that a push

event at the PB pin must satisfy before it is recognized as

a valid pushbutton on or off.

ONT

= C

ONT

• (9.3MΩ)

OFFT

= C

OFFT

• (9.3MΩ)

ONT

and C

OFFT

are the ONT and OFFT external program-

ming capacitors respectively.

Note that during the push event of the pushbutton off, the

INT pin is asserted low after the initial 26ms debounce

duration. The INT pin asserts low when the PB pin is

held low during the OFFT debounce duration and during

the shutdown sequence. If the PB pin pulls high before

the OFFT time ends, the INT pin immediately turns high

impedance. On the other hand, if the PB pin is still held

low at the end of the OFFT time, the INT pin continues to

assert low throughout the ensuing shutdown sequence.

On a release event (rising edge) of the pushbutton switch

following a valid push event, the PB pin must be continu-

ously held above its rising threshold (0.8V) for a fixed

26ms internal debounce time.

In a typical application, the PB pin is connected to a

pushbutton switch. If the switch exhibits high leakage

current (>10μA), connecting an external pull-up resistor

to V1, V2 and/or VS (depending on the application) is

recommended. Furthermore, if the pushbutton switch is

physically located far from the LTC2952’s PB pin, signals

may couple onto the high impedance PB input. Placing

a 0.1μF capacitor from the PB pin to ground reduces the

impact of signal coupling. Additionally, parasitic series

inductance may cause undesirable ringing at the PB pin.

This can be minimized by placing a 5k resistor in series

and located next to the switch.

Figure 8. Pushbutton Debounce Timing Diagram

2952 F08

ONT CAP

OFFT CAP

INTERNAL

ON/OFF SIGNAL

OFFT

ONT

DB,OFF

26ms

OFFT

DB,OFF

26ms

DB,ON

26ms

DB,ON

26ms

DB,OFF

26ms

DB,ON

26ms

DB,OFF

26ms

INVALID PB

PUSH EVENT

VALID PB

‘TURN-OFF’ EVENT

VALID PB

‘TURN-ON’ EVENT

INVALID PB

PUSH EVENT

INVALID PB

RELEASE EVENT

INT

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

LTC2952IF#TRPBF

Mfr. #:

Buy LTC2952IF#TRPBF

Manufacturer:

Analog Devices Inc.

Description:

Power Management Specialized - PMIC Push Button Power Path Controller with System Monitoring

Lifecycle:

New from this manufacturer.

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LTC2952IF#TRPBF

LTC2952IF#TRPBF

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