19/30
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 20. AC Characteristics (M93Cx6-W, temperature range 6)
Note: 1. t
CHCL
+ t
CLCH
1 / f
C
.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. Current product: identified by Process Identification letter F or M.
4. New product: identified by Process Identification letter W.
Test conditions specified in Table 12 and Table 9
Symbol Alt. Parameter
Min.
3
Max.
3
Min.
4
Max.
4
Unit
f
C
f
SK
Clock Frequency D.C. 1 D.C. 2 MHz
t
SLCH
Chip Select Low to Clock High 250 50 ns
t
SHCH
t
CSS
Chip Select Set-up Time 100 50 ns
t
SLSH
2
t
CS
Chip Select Low to Chip Select High 1000 200 ns
t
CHCL
1
t
SKH
Clock High Time 350 200 ns
t
CLCH
1
t
SKL
Clock Low Time 250 200 ns
t
DVCH
t
DIS
Data In Set-up Time 100 50 ns
t
CHDX
t
DIH
Data In Hold Time 100 50 ns
t
CLSH
t
SKS
Clock Set-up Time (relative to S) 100 50 ns
t
CLSL
t
CSH
Chip Select Hold Time 0 0 ns
t
SHQV
t
SV
Chip Select to Ready/Busy Status 400 200 ns
t
SLQZ
t
DF
Chip Select Low to Output Hi-Z 200 100 ns
t
CHQL
t
PD0
Delay to Output Low 400 200 ns
t
CHQV
t
PD1
Delay to Output Valid 400 200 ns
t
W
t
WP
Erase/Write Cycle time 10 5 ms
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
20/30
Table 21. AC Characteristics (M93Cx6-W, temperature range 7 or 3)
Note: 1. t
CHCL
+ t
CLCH
1 / f
C
.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. New product: identified by Process Identification letter W.
Test conditions specified in Table 12 and Table 9
Symbol Alt. Parameter
Min.
3
Max.
3
Unit
f
C
f
SK
Clock Frequency D.C. 2 MHz
t
SLCH
Chip Select Low to Clock High 50 ns
t
SHCH
t
CSS
Chip Select Set-up Time 50 ns
t
SLSH
2
t
CS
Chip Select Low to Chip Select High 200 ns
t
CHCL
1
t
SKH
Clock High Time 200 ns
t
CLCH
1
t
SKL
Clock Low Time 200 ns
t
DVCH
t
DIS
Data In Set-up Time 50 ns
t
CHDX
t
DIH
Data In Hold Time 50 ns
t
CLSH
t
SKS
Clock Set-up Time (relative to S) 50 ns
t
CLSL
t
CSH
Chip Select Hold Time 0 ns
t
SHQV
t
SV
Chip Select to Ready/Busy Status 200 ns
t
SLQZ
t
DF
Chip Select Low to Output Hi-Z 100 ns
t
CHQL
t
PD0
Delay to Output Low 200 ns
t
CHQV
t
PD1
Delay to Output Valid 200 ns
t
W
t
WP
Erase/Write Cycle time 5 ms
21/30
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 22. AC Characteristics (M93Cx6-R)
Note: 1. t
CHCL
+ t
CLCH
1 / f
C
.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. This product is under development. For more infomation, please contact your nearest ST sales office.
Test conditions specified in Table 12 and Table 10
Symbol Alt. Parameter
Min.
3
Max.
3
Unit
f
C
f
SK
Clock Frequency D.C. 1 MHz
t
SLCH
Chip Select Low to Clock High 250 ns
t
SHCH
t
CSS
Chip Select Set-up Time 50 ns
t
SLSH
2
t
CS
Chip Select Low to Chip Select High 250 ns
t
CHCL
1
t
SKH
Clock High Time 250 ns
t
CLCH
1
t
SKL
Clock Low Time 250 ns
t
DVCH
t
DIS
Data In Set-up Time 100 ns
t
CHDX
t
DIH
Data In Hold Time 100 ns
t
CLSH
t
SKS
Clock Set-up Time (relative to S) 100 ns
t
CLSL
t
CSH
Chip Select Hold Time 0 ns
t
SHQV
t
SV
Chip Select to Ready/Busy Status 400 ns
t
SLQZ
t
DF
Chip Select Low to Output Hi-Z 200 ns
t
CHQL
t
PD0
Delay to Output Low 400 ns
t
CHQV
t
PD1
Delay to Output Valid 400 ns
t
W
t
WP
Erase/Write Cycle time 10 ms

M93C46-RDS6G

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
EEPROM 1K (64x8 or 32x16)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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