Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. 0 | Page 19 of 23
25
20
15
10
5
0
0 20 40 60 80 100 120 140 160
I
DD1
SUPPLY CURRENT (mA)
DATA RATE (Mbps)
5V
3.3V
2.5V
1.8V
14998-016
Figure 16. ADuM263N I
DD1
Supply Current vs. Data Rate at Various Voltages
25
20
15
10
5
0
0 20 40 60 80 100 120 140 160
5V
3.3V
2.5V
1.8V
I
DD2
SUPPLY CURRENT (mA)
DATA RATE (Mbps)
14998-017
Figure 17. ADuM263N I
DD2
Supply Current vs. Data Rate at Various Voltages
14
12
10
8
6
4
2
0
40200 20406080 120100 140
PROPAGATION DELAY
t
PLH
(ns)
TEMPERATURE (°C)
5V
3.3V
2.5V
1.8V
14998-018
Figure 18. Propagation Delay, t
PLH
vs. Temperature at Various Voltages
14
12
10
8
6
4
2
0
40200 20406080 120100 140
PROPAGATION DELAY
t
PHL
(ns)
TEMPERATURE (°C)
5V
3.3V
2.5V
1.8V
14998-019
Figure 19. Propagation Delay, t
PHL
vs. Temperature at Various Voltages
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. 0 | Page 20 of 23
THEORY OF OPERATION
The ADuM260N/ADuM261N/ADuM262N/ADuM263N use
a high frequency carrier to transmit data across the isolation
barrier using iCoupler chip scale transformer coils separated by
layers of polyimide isolation. Using an on/off keying (OOK)
technique and the differential architecture shown in Figure 20
and Figure 21, the ADuM260N/ADuM261N/ADuM262N/
ADuM263N have very low propagation delay and high speed.
Internal regulators and input/output design techniques allow
logic and supply voltages over a wide range from 1.7 V to 5.5 V,
offering voltage translation of 1.8 V, 2.5 V, 3.3 V, and 5 V logic.
The architecture is designed for high common-mode transient
immunity and high immunity to electrical noise and magnetic
interference. Radiated emissions are minimized with a spread
spectrum OOK carrier and other techniques.
Figure 20 shows the waveforms for models of the ADuM260N0/
ADuM261N0/ADuM262N0/ADuM263N0 that have the
condition of the fail-safe output state equal to low, where the
carrier waveform is off when the input state is low. If the input
side is off or not operating, the fail-safe output state of low sets
the output to low. For the ADuM260N1/ADuM261N1/
ADuM262N1/ADuM263N1 that have a fail-safe output state of
high, Figure 21 illustrates the conditions where the carrier
waveform is off when the input state is high. When the input
side is off or not operating, the fail-safe output state of high sets
the output to high. See the Ordering Guide for the model
numbers that have the fail-safe output state of low or the fail-safe
output state of high.
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
14998-020
Figure 20. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
14998-021
Figure 21. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. 0 | Page 21 of 23
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM260N/ADuM261N/ADuM262N/ADuM263N digital
isolators require no external interface circuitry for the logic
interfaces. Power supply bypassing is strongly recommended at
the input and output supply pins (see Figure 22). Bypass
capacitors are connected between Pin 1 and Pin 8 for V
DD1
and
between Pin 9 and Pin 16 for V
DD2
. The recommended bypass
capacitor value is between 0.01 μF and 0.1 μF. The total lead
length between both ends of the capacitor and the input power
supply pin must not exceed 10 mm.
V
DD1
V
IA
V
IB
V
IC
V
ID
, V
OD
V
IE
, V
OE
V
IF
, V
OF
GND
1
V
DD2
V
OA
V
OB
V
OC
V
ID
, V
OD
V
IE
, V
OE
V
IF
, V
OF
GND
2
14998-022
Figure 22. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the Absolute Maximum Ratings of the device,
thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
14998-023
Figure 23. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel matching is the maximum amount the propagation
delay differs between channels within a single ADuM260N/
ADuM261N/ADuM262N/ADuM263N component.
Propagation delay skew is the maximum amount the propagation
delay differs between multiple ADuM260N/ADuM261N/
ADuM262N/ADuM263N components operating under the
same conditions.
JITTER MEASUREMENT
Figure 24 illustrates the eye diagram for the ADuM260N/
ADuM261N/ADuM262N/ADuM263N. The measurement was
taken using an Agilent 81110A pulse pattern generator at 150 Mbps
with pseudorandom bit sequences (PRBS) 2(n − 1), n = 14, for 5 V
supplies. Jitter was measured with the Tektronix Model 5104B
oscilloscope, 1 GHz, 10 GSPS with the DPOJET jitter and eye
diagram analysis tools. The result shows a typical measurement
on the ADuM260N/ADuM261N/ADuM262N/ADuM263N
with 490 ps p-p jitter.
105
0
1
2
3
4
VOLTAGE (V)
5
0
TIME (ns)
–5–10
14998-024
Figure 24. ADuM260N/ADuM261N/ADuM262N/ADuM263N Eye Diagram
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking,
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation, pollution degree, and material group. The material
group and creepage for the ADuM260N/ADuM261N/
ADuM262N/ADuM263N isolators are presented in Table 9.

ADUM262N1BRIZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators Robust 5kV 6 CH Digital ISO 4/2
Lifecycle:
New from this manufacturer.
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