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6V49205BPAGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
REVISION R 11/23/16 7 FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY
6V49205B DATASHEET
Electrical Characteristics - DDR Clock
Electrical Characteristics - Sys_CCB
Electrical Characteristics - 125M
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
f
DDR66.66
SEL100#_66 = 1, V
T
= OVDD/2 V MHz 2,3,6
f
DDR100
SEL100#_66 = 0, V
T
= OVDD/2 V MHz 2,3,6
ppm
SSof f
Spread off ppm 1,2,5
ppm
SSon
Spread on ppm 1,2,5
Output High Voltage V
OH
V
OH
at the selected operating frequency 2.4 V 1
Output Low Voltage V
OL
V
OL
at the selected operating frequency 0.4 V 1
t
SLEW00
'00' = Hi-Z V/ns
t
SLEW01
'01' Slow Slew Rate (Averaging on) 1.1 1.6 2.3 V/ns 1,3,8
t
SLEW10
'10' Fast Slew Rate (Averaging on) 1.6 2.3 3.2 V/ns 1,3,8
t
SLEW11
'11' Fastest Slew Rate (Averaging on) 1.8 2.7 3.7 V/ns 1,3,8
Duty Cycle d
t1
V
T
= OVDD/2 V 40 51.4 60 % 1,6
Jitter, Peak period jitter t
jpeak
V
T
= OVDD/2 V ±96 ±150 ps 1,6
Phase Noise t
phasenoise
-56dBc 10 500 kHz 1,7
AC Input Swing Limits @ 3.3V
OV
DD
V
AC
This is the difference between VOL and
VOH at the selected operating frequency.
1.9 3.4 V 1
Spread Spectrum Modulation
Frequency
f
SSMOD
Triangular Modulation 30 32.3 60 kHz
Slew Rate
VDDO = 3.3V
Hi-Z
DDR Clock Frequency
66.666
100.00
Synthesis error
0
+/-150
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
FS(1:0) = 00, VT = OVDD/2 V MHz 2,3,6
FS(1:0) = 01, VT = OVDD/2 V MHz 2,3,6
FS(1:0) = 10, VT = OVDD/2 V MHz 2,3,6
FS(1:0) = 11, VT = OVDD/2 V MHz 2,3,6
ppm
SSof f
Spread off ppm 1,2,5
ppm
SSon
Spread on ppm 1,2,5
Output High Voltage V
OH
V
OH
at the selected operating frequency 2.4 V 1
Output Low Voltage V
OL
V
OL
at the selected operating frequency 0.4 V 1
t
SLEW00
'00' = Hi-Z V/ns
t
SLEW01
'01' Slow Slew Rate (Averaging on) 0.8 1.4 2.1 V/ns 1,3,8
t
SLEW10
'10' Fast Slew Rate (Averaging on) 0.9 1.6 2.5 V/ns 1,3,8
t
SLEW11
'11' Fastest Slew Rate (Averaging on) 1.1 1.9 3.1 V/ns 1,3,8
Duty Cycle d
t1
V
T
= OVDD/2 V 40 51.4 60 % 1,6
Jitter, Peak period jitter t
jpeak
V
T
= OVDD/2 V, SSC < 0.75% ±116
±
150 ps 1
Phase Noise t
phasenoise
-56dBc 10 500 kHz 1,7
AC Input Swing Limits @ 3.3V
OV
DD
V
AC
This is the difference between VOL and
VOH at the selected operating frequency.
1.9 V 1
Spread Spectrum Modulation
Frequency
f
SSMOD
Triangular Modulation 0 31.5 60 kHz
Hi-Z
Slew Rate
VDDO = 3.3V
83.333
Synthesis error
0
+/-150
Clock Frequency f
Sy s_CCB
66.666
100.00
80.00
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Clock frequency f
125M
V
T
= OVDD/2 V ns 2,3,6
Synthesis error ppm ppm 1,2,5
Output High Voltage V
OH
V
OH
at the selected operating frequency 2.2 V 1
Output Low Voltage V
OL
V
OL
at the selected operating frequency 0.5 V 1
Rise/Fall time
VDDO = 3.3V
t
RF125M3.3V
Measured between 0.6V and 2.7V 0.7 1 ns 1,3
Duty Cycle d
t1
V
T
= OVDD/2 V 47 52 53 % 1
Jitter, Peak period jitter t
jpeak
V
T
= OVDD/2 V
±
150 ps 1
0
125.00
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY 8 REVISION R 11/23/16
6V49205B DATASHEET
Electrical Characteristics - REF(5:0)
Electrical Characteristics - USB_CLK(2:1)
Electrical Characteristics - 2.048M(1:0)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Clock Frequency f V
T
= OVDD/2 V MHz 2,3
Crystal Frequency Error ppm Including all aging and tuning effects -50 50 ppm 1,2
Output High Voltage
V
OH
V
OH
at the selected operating frequency
2.2 V 1
Output Low Voltage V
OL
V
OL
at the selected operating frequency 0.4 V 1
Slew Rate
VDDO 3 3V
t
SLEW
'00' = Hi-Z 1.0 1.7 2.7 V/ns 1,3,4
Duty Cycle d
t1
V
T
= OVDD/2 V 40 51 60 % 1
Pin to Pin Skew t
skew
V
T
= 1.5 V, odd/even outputs have an
intentional 180degree phase shift.
ps 1
Jitter, Peak period jitter t
jpeak
V
T
= OVDD/2 V ±78 ±200 ps 1
Jitter, Phase t
jphase
(12kHz-5MHz), V
T
= 1.5 V 1.7 3 ps rms 1
N/A
25.00
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
MHz 2,3
MHz 2,3
Synthesis error ppm ppm 1,2,5
Output High Voltage V
OH
V
OH
at the selected operating frequency 2.2 V 1
Output Low Voltage V
OL
V
OL
at the selected operating frequency 0.4 V 1
t
SLEW00
'00' = Hi-Z V/ns
t
SLEW01
'01' Slow Slew Rate (Averaging on) 1.0 1.4 1.8 V/ns 1,3,4
t
SLEW10
'10' Fast Slew Rate (Averaging on) 1.5 2.0 2.7 V/ns 1,3,4
t
SLEW11
'11' Fastest Slew Rate (Averaging on) 1.8 2.3 3.1 V/ns 1,3,4
Duty Cycle d
t1
V
T
= OVDD/2 V 45 50.3 55 % 1
Jitter, RMS t
jRMS
12kHz to Nyquist 23 120 ps 1
Jitter, Cycle to cycle t
jcyc-cyc
V
T
= OVDD/2 V 142 350 ps 1
Slew Rate
VDDO = 3.3V
Hi-Z
24.00
0
Clock Frequency f
USB_CLK
V
T
= OVDD/2 V
12.00
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Clock Frequency f
USB_CLK
V
T
= OVDD/2 V MHz 2,3,6
Synthesis error ppm ppm 1,2,5
Output High Voltage V
OH
V
OH
at the selected operating frequency 2.2 V 1
Output Low Voltage V
OL
V
OL
at the selected operating frequency 0.4 V 1
t
SLEW00
'00' = Hi-Z V/ns
t
SLEW01
'01' Slow Slew Rate (Averaging on) 1.1 1.7 2.5 V/ns 1,3,4
t
SLEW10
'10' Fast Slew Rate (Averaging on) 1.6 2.3 3.2 V/ns 1,3,4
t
SLEW11
'11' Fastest Slew Rate (Averaging on) 1.8 2.6 3.6 V/ns 1,3,4
Duty Cycle d
t1
V
T
= OVDD/2 V 45 46.7 55 % 1
Pin to Pin Skew t
skew
V
T
= OVDD/2 V 108 250 ps 1
Jitter, RMS t
jRMS
12kHz to Nyquist 47 70 ps 1
Jitter, Peak period jitter t
jpeak
V
T
= OVDD/2 V ±170 ±250 ps 1
Notes for single-ended clocks:
1
Guaranteed by design and characterization, not 100% tested in production.
2
Clock Frequency specifications are guaranteed assuming that REF is at 25MHz
3
At default SMBus settings
4
Measured betweeen 20% and 80% of OVDD
5
This is the frequency error with respect to the crystal frequency.
6
Measured at the rising and/or falling edge at OVDD/2 V.
7
Phase noise is calculated as the FFT of the TIE jitter.
8
Slew rate is measured from ±0.3
Δ
V
AC
at the center of peak to peak voltage at the clock input.
Hi-Z
Slew Rate
VDDO = 3.3V
2.048
0
REVISION R 11/23/16 9 FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY
6V49205B DATASHEET
General SMBus Serial Interface Information for 6V49205B
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Note: I
2
C compatible. Native mode is SMBus Block mode
protocol. To use I
2
C Byte mode set the 2^7 bit in the
command Byte. No Byte count is used.
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address D2
(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address D2
(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address D3
(H)
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

6V49205BPAGI

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Buy 6V49205BPAGI
Manufacturer:
IDT
Description:
Clock Generators & Support Products Clock Generator P1020 P2020 P2040
Lifecycle:
New from this manufacturer.
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