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NB7L11MMNR2G

P1-P3P4-P6P7-P9P10-P11
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 4
1 Publication Order Number:
NB7L11M/D
NB7L11M
2.5V/3.3V Differential
1:2 Clock/Data Fanout
Buffer/Translator with CML
Outputs and Internal
Termination
Description
The NB7L11M is a differential 1-to-2 clock/data distribution chip
with internal source termination and CML output structure, optimized
for low skew and minimal jitter. The device is functionally equivalent to
the EP11, LVEP11, or SG11 devices. Device produces two identical
output copies of clock or data operating up to 8 GHz or 12 Gb/s,
respectively. As such, NB7L11M is ideal for SONET, GigE, Fiber
Channel, Backplane and other clock/data distribution applications.
Inputs incorporate internal 50 W termination resistors and accept
LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6).
Differential 16 mA CML output provides matching internal 50ĂW
terminations, and 400 mV output swings when externally terminated,
50 W to V
CC
(See Figure 14).
The device is offered in a low profile 3x3 mm 16-pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
• Maximum Input Clock Frequency up to 8 GHz Typical
• Maximum Input Data Rate up to 12 Gb/s Typical
• < 0.5 ps of RMS Clock Jitter
• < 10 ps of Data Dependent Jitter
• 30 ps Typical Rise and Fall Times
• 110 ps Typical Propagation Delay
• 3 ps Typical Within Device Skew
• Operating Range: V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
• CML Output Level (400 mV Peak-to-Peak Output) Differential
Output Only
• 50 W Internal Input and Output Termination Resistors
• Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
Figure 1. Logic Diagram
Q0
Q0
Q1
Q1
V
TCLK
CLK
CLK
V
TCLK
50 W
50 W
MARKING DIAGRAM*
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb-Free Package
QFN−16
MN SUFFIX
CASE
485G−01
www.onsemi.com
(Note: Microdot may be in either location)
NB7L
11M
ALYWG
G
1
*For additional marking information, refer to
Application Note AND8002/D
.
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
ORDERING INFORMATION
Device Package Shipping
†
NB7L11MMNG QFN−16
(Pb-Free)
123 Units/Tube
NB7L11MMNR2G QFN−16
(Pb-Free)
3000/Tape & Reel
NB7L11M
www.onsemi.com
2
V
CC
Q1 Q1 V
CC
V
CC
Q0 Q0 V
CC
V
EE
V
EE
V
EE
V
EE
V
TCLK
CLK
CLK
V
TCLK
5678
16 15 14 13
12
11
10
9
1
2
3
4
NB7L11M
Exposed Pad (EP)
Figure 2. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 V
TCLK
−
Internal 50 W Termination Pin for CLK
2 CLK LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Inverted Differential Clock/Data Input. (Note 1)
3 CLK LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Non−inverted Differential Clock/Data Input. (Note 1)
4 V
TCLK
−
Internal 50 W Termination Pin for CLK
5,8,13,16 V
CC
− Positive Supply Voltage. All V
CC
pins must be externally connected to a Power Supply
to guarantee proper operation.
6 Q1 CML Output
Inverted CLK output 1 with internal 50 W source termination resistor. (Note 2)
7 Q1 CML Output
Non−inverted CLK output 1 with internal 50 W source termination resistor. (Note 2)
9,10,11,12 V
EE
− Negative Supply Voltage. All V
EE
pins must be externally connected to a Power Supply
to guarantee proper operation.
14 Q0 CML Output
Inverted CLK output 0 with internal 50 W source termination resistor. (Note 2)
15 Q0 CML Output
Non−inverted CLK output 0 with internal 50 W source termination resistor. (Note 2)
− EP − Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must
be attached to a heatsinking conduit. It is recommended to connect the EP to the lower
potential (V
EE
).
1. In the differential configuration when the input termination pins (V
TCLK
, V
TCLK
) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK
then the device will be susceptible to self-oscillation.
2. CML outputs require 50 W receiver termination resistor to V
CC
for proper operation.
NB7L11M
www.onsemi.com
3
Table 2. ATTRIBUTES
Characteristics Value
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1500 V
> 50 V
> 500 V
Moisture Sensitivity (Note 1) Pb-Free Pkg
QFN-16 Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count 285
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply V
EE
= 0 V 3.6 V
V
I
Input Voltage V
EE
= 0 V V
EE
ĂV V
I
ĂV V
CC
3.6 V
V
INPP
Differential Input Voltage |CLK − CLK| V
CC
− V
EE
w 2.8 V
V
CC
− V
EE
< 2.8 V
2.8
|V
CC
− V
EE
|
V
I
IN
Input Current Through R
T
(50 W Resistor)
Static
Surge
45
80
mA
I
out
Output Current Continuous
Surge
25
50
mA
T
A
Operating Temperature Range QFN−16 −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient)
(Note 1)
0 lfpm
500 lfpm
QFN−16 42
36
°C/W
q
JC
Thermal Resistance (Junction-to-Case) 2S2P (Note 1) QFN−16 3 to 4 °C/W
T
sol
Wave Solder (Pb-Free) 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
P1-P3P4-P6P7-P9P10-P11

NB7L11MMNR2G

Mfr. #:
Buy NB7L11MMNR2G
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 2.5V/3.3V Multilevel 1:2 Clock / Fanout
Lifecycle:
New from this manufacturer.
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