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NB7L11MMNR2G

P1-P3P4-P6P7-P9P10-P11
NB7L11M
www.onsemi.com
7
Figure 8. AC Reference Measurement
CLK
CLK
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(CLK) − V
IL
(CLK)
V
OUTPP
= V
OH
(Q) − V
OL
(Q)
Figure 9. Typical Termination for Output Driver Using External Termination Resistor
(Refer to Application Notes AND8020/D
and AND8173/D)
NB7L11M
Receiver
Device
Q CLK
Q CLK
V
CC
50 W50 W
V
CC
50 W50 W
Z = 50 W
Z = 50 W
Figure 10. Differential Input Driven
Single-Ended
Figure 11. Differential Inputs Driven
Differentially
Figure 12. V
th
Diagram Figure 13. V
CMR
Diagram
CLK
V
CC
GND
V
IH
V
IHmin
V
IHmax
V
thmax
V
th
V
th
V
thmin
V
CMmax
V
CMmax
CLK
V
CMR
V
CC
GND
CLK
CLK
V
th
V
th
CLK
CLK
V
ILmax
V
IL
V
ILmin
CLK
V
ILCLKmax
V
IHCLKmax
V
(CLK)
= V
IHCLK
− V
ILCLK
V
ILCLKtyp
V
IHCLKtyp
V
ILCLKmin
V
IHCLKmin
NB7L11M
www.onsemi.com
8
Q
Q
V
CC
16 mA
50 W50 W
Figure 14. CML Output Structure
V
EE
Table 6. INTERFACING OPTIONS
INTERFACING OPTIONS CONNECTIONS
CML Connect V
TCLK
, V
TCLK
to V
CC
LVDS Connect V
TCLK
, V
TCLK
together CLK input
AC-COUPLED Bias V
TCLK
, V
TCLK
Inputs within (V
CMR
) Common Mode Range
RSECL, LVPECL Standard ECL Termination Techniques. See AND8020/D.
LVTTL, LVCMOS An external voltage should be applied to the unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and V
CC
/2 for LVCMOS inputs.
NB7L11M
www.onsemi.com
9
Application Information
All NB7L11M inputs can accept PECL, CML, LVTTL,
LVCMOS and LVDS signal levels. The limitations for
differential input signal (LVDS, PECL, or CML) are
minimum input swing of 75 mV and the maximum input
swing of 2500 mV. Within these conditions, the input
voltage can range from V
CC to 1.2 V. Examples interfaces
are illustrated below in a 50 W environment (Z = 50 W).
50 W
V
CC
CLK
CLK
50 W
NB7L11M
V
CC
V
TCLK
V
EE
V
CC
Q
50 W 50 W
CML Driver
V
EE
Figure 15. CML to CML Interface
Z
Q
Z
Figure 16. PECL to CML Receiver Interface
50 W
Z
Z
V
CC
V
CC
PECL
Driver
CLK
CLK
50 W
NB7L11M
V
EE
V
Bias
V
TCLK
V
EE
R
T
R
T
V
EE
V
CC
R
T
5.0 V
290 W
3.3 V
150 W
2.5 V
80 W
Recommended R
T
Values
50 W
50 W
V
TCLK
V
CC
V
TCLK
V
Bias
P1-P3P4-P6P7-P9P10-P11

NB7L11MMNR2G

Mfr. #:
Buy NB7L11MMNR2G
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 2.5V/3.3V Multilevel 1:2 Clock / Fanout
Lifecycle:
New from this manufacturer.
Delivery:
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