11
LTC1875
1875f
C
IN
and C
OUT
Selection
In continuous mode, the source current of the top MOSFET
is a trapezoidal waveform of duty cycle V
OUT
/V
IN
. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS input capacitor current is given by:
II
VVV
V
RMS CIN OMAX
OUT IN OUT
IN
()
/
(– )
≅
[]
12
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant devia-
tions do not offer much relief. Note that the capacitor
manufacturer’s ripple current ratings are often based on
2000 hours of life. This makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in
the design. Always consult the manufacturer if there are
any questions.
Depending on how the LTC1875 circuit is powered up,
you may need to check for input voltage transients. Input
voltage transients may be caused by input voltage steps
or by connecting the circuit to an already powered up
source such as a wall adapter. The sudden application of
input voltage will cause a large surge of current in the
input leads that will store energy in the parasitic induc-
tance of the leads. This energy will cause the input voltage
to swing above the DC level of the input power source and
it may exceed the maximum voltage rating of the input
capacitor and LTC1875.
The easiest way to suppress input voltage transients is to
add a small aluminum electrolytic capacitor in parallel
with the low ESR input capacitor. The selected capacitor
needs to have the right amount of ESR in order to critically
dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESR will fall in the range of 0.5Ω to 2Ω and capacitance
will fall in the range of 5µF to 50µF.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfied, the capacitance is adequate for filtering.
The output ripple ∆V
OUT
is determined by:
∆≅∆ +
V I ESR
fC
OUT L
OUT
1
8
where f = operating frequency, C
OUT
= output capacitance
and ∆I
L
= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆I
L
increases
with input voltage. For the LTC1875, the general rule for
proper operation is:
ESR
COUT
< 0.125Ω
The choice of using a smaller output capacitance in-
creases the output ripple voltage due to the frequency
dependent term but can be compensated for by using
capacitor(s) of very low ESR to maintain low ripple volt-
age. The I
TH
pin compensation components can be opti-
mized to provide stable high performance transient
response regardless of the output capacitor selected.
Manufacturers such as Taiyo Yuden, AVX, Kemet and
Sanyo should be considered for low ESR, high perfor-
mance capacitors. The POSCAP solid electrolytic chip
capacitor available from Sanyo is an excellent choice for
output bulk capacitors due to its low ESR/size ratio. Once
the ESR requirement for C
OUT
has been met, the RMS
current rating generally far exceeds the I
RIPPLE(P-P)
requirement.
Output Voltage Programming
The output voltage is set by a resistor divider according to
the following formula:
VV
R
R
OUT
=+
08 1
1
2
.
(2)
The external resistor divider is connected to the output,
allowing remote voltage sensing as shown in Figure 4.
APPLICATIO S I FOR ATIO
WUUU
