DS1077LU-40+ Datasheet DS1077LU-40+, DS1077LU-66+, DS1077LZ-50 | P7-P9

DS1077L

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TABLE 5

BIT VALUE DIVISOR (N)

0 000 000 000*

0 0 00 0 00 001 3

— —

1 111 111 111 1025

*Default Condition

BUS WORD

NAME — — — — WC A2 A1 A0

Factory Default 0* 0* 0* 0* 0 0 0 0

*These bits are reserved and must be set to zero.

A0, A1, A2 (Default Setting = 000)

These are the device select bits that determine the address of the device.

WC (Default Setting WC = 0)

This bit determines when/if the EEPROM is written to after register contents have been changed.

If WC = 0, the EEPROM is automatically written after a write register command.

If WC = 1, the EEPROM is only written when the WRITE command is issued.

Regardless of the value of the WC bit, when the BUS register (A0, A1, A2) is written, the current value in

all registers (DIV, MUX, and BUS) are immediately written to the EEPROM.

2-WIRE SERIAL DATA BUS

The DS1077L supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls

the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must

be controlled by a master device that generates the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions. The DS1077L operates as a slave on the 2-wire bus.

Connections to the bus are made via the open-drain I/O lines, SDA and SCL. A pullup resistor (5k) is

connected to SDA.

The following bus protocol has been defined (see Figure 2):

§ Data transfer may be initiated only when the bus is not busy.

§ During data transfer, the data line must remain stable whenever the clock line is high. Changes in

the data line while the clock line is high will be interpreted as control signals.

DS1077L

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Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain high.

Start data transfer: A change in the state of the data line from high to low while the clock is high

defines a START condition.

Stop data transfer: A change in the state of the data line from low to high while the clock line is high

defines the STOP condition.

Data valid: The state of the data line represents valid data when, after a START condition, the data line is

stable for the duration of the HIGH period of the clock signal. The data on the line must be changed

during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions is not limited, and is determined

by the master device. The information is transferred byte-wise and each receiver acknowledges with a

ninth bit.

Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate)

are defined. The DS1077L works in both modes.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the

reception of each byte. The master device must generate an extra clock pulse which is associated with this

acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of

course, setup and hold times must be taken into account. When the DS1077L EEPROM is being written

to, it will not be able to perform additional responses. In this case, the slave DS1077L will send a ‘not

acknowledge’ to any data transfer request made by the master. It will resume normal operation when the

EEPROM operation is complete.

A master must signal an end-of-data to the slave by not generating an acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the

master to generate the STOP condition.

DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 2

MSB

slave address

R/W

direction

bit

SDA

SCL

START

CONDITION

12 6789

12 89

STOP CONDITION

REPEATED

START CONDITION

3 - 8

acknowledgement

signal from receiver

acknowledgement

signal from receiver

ACK ACK

repeated if more bytes

are transferred

DS1077L

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Figure 2 details how data transfer is accomplished on the 2-wire bus. Depending upon the state of the

R/W bit, two types of data transfer are possible:

1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the

master is the slave address. Next, follows a number of data bytes. The slave returns an acknowledge

bit after each received byte.

2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is

transmitted by the master. The slave then returns an acknowledge bit. Next, follows a number of data

bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received

bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned.

The master device generates all of the serial clock pulses and the START and STOP conditions. A

transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START

condition is also the beginning of the next serial transfer, the bus will not be released.

The DS1077L can operate in the following two modes:

1) Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is

received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the

beginning and end of a serial transfer. Address recognition is performed by hardware after reception

of the slave address and direction bit.

2) Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.

However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data

is transmitted on SDA by the DS1077L while the serial clock is input on SCL. START and STOP

conditions are recognized as the beginning and end of a serial transfer.

SLAVE ADDRESS

A control byte is the first byte received following the START condition from the master device. The

control byte consists of a four-bit control code; for the DS1077L, this is set as 1011 binary for read and

write operations. The next three bits of the control byte are the device select bits (A2, A1, and A0) and

can be written to the EEPROM. They are used by the master device to select which of eight devices are to

be accessed. The select bits are in effect the three least significant bits of the slave address. The last bit of

the control byte (R/

W ) defines the operation to be performed. When set to a one a read operation is

selected, and when set to a zero a write operation is selected. Following the START condition, the

DS1077L monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the

1011 code (changeable with one mask) and appropriate device select bits, the slave device outputs an

acknowledge signal on the SDA line.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

DS1077LU-40+

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Clock Generators & Support Products EconOscillator/Dvdr 40Mhz 118mil 2-Wire

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DS1077LU-40+

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