DS1077L
10 of 21
2-WIRE SERIAL COMMUNICATION WITH DS1077L Figure 3
1S
1
C00
1
WAP
SDA
SCL
Address Byte Command ByteStart DS1077L
ACK
StopDS1077L
ACK
Send a “Standalone” Command
C1C2C3C4C5C6C7AA2 A1 A0
Write MSB of a Two-Byte Register
1S C00 WA
SDA
SCL
Address Byte Command ByteStart DS1077L
ACK
DS1077L
ACK
C1C2C3C4C5C6C7A D0 AP
MSByte StopDS1077L
ACK
D1D2D3D4D5D6D7
1S C00 WA
SDA
SCL
Address Byte Command ByteStart DS1077L
ACK
DS1077L
ACK
Write to a Two-Byte Register
C1C2C3C4C5C6C7A D0
MSByte
D1D2D3D4D5D6D7 A
DS1077L
ACK
D0 AP
LSByte StopDS1077L
ACK
D1D2D3D4D5D6D7
1S C00 WA
SDA
SCL
Control Byte Command ByteStart DS1077L
ACK
DS1077L
ACK
Write a Single Byte to an Addressed Register
C1C2C3C4C5C6C7A A0
Byte Address
A1A2A3A4A5A6A7 A
DS1077L
ACK
D0 AP
Data Byte StopDS1077L
ACK
D1D2D3D4D5D6D7
Byte (n+1)
D1D2D3D4D5D6
SDA
SCL
D7
Byte N
D1D2D3D4D5D6D7D0 A
DS1077L
ACK
D0 AP
StopDS1077L
ACK
1S C00 WA
SDA
SCL
Control Byte Command ByteStart DS1077L
ACK
DS1077L
ACK
Write Multiple Bytes to an Addressed Register
C1C2C3C4C5C6C7A A0
Starting Byte Address
A1A2A3A4A5A6A7 A
DS1077L
ACK
D0 A
Byte n DS1077L
ACK
D1D2D3D4D5D6D7
11A2
A1
A0
11A2
A1
A0
11A2
A1
A0
11A2
A1
A0
DS1077L
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2-WIRE SERIAL COMMUNICATION WITH DS1077L Figure 3 (cont.)
1S 1 C001 W
SDA
SCL
Control Byte Command ByteStart DS1077L
ACK
Read Single Byte Register or MSB from a Two-Byte Register
C1C2C3C4C5C6C7A 1R 01 Rd A
Control ByteRepeated
Start
DS1077L
ACK
A
DS1077L
ACK
NP
MSByte StopMaster
NACK
D1D2D3D4D5D6 D0D7A2 A1 A0 1A2A1A0
NP
LSByte StopMaster
NACK
D1D2D3D4D5D6 D0
SDA
SCL
D7
1S C001 W
SDA
SCL
Control Byte Command ByteStart DS1077L
ACK
Read from a Two-Byte Register
C1C2C3C4C5C6C7A 1R 01 A
Control ByteRepeated
Start
DS1077L
ACK
A
DS1077L
ACK
A
MSByte Master
ACK
D1D2D3D4D5D6D7 D01 A2 A1 A0 Rd1A2A1A0
1S 1 C001 W
SDA
SCL
Control Byte Command ByteStart DS1077L
ACK
Read Multiple Bytes from an Addressed Register
C1C2C3C4C5C6C7A A
DS1077L
ACK
A2 A1 A0 1R 01 Rd A
Control ByteRepeated
Start
DS1077L
ACK
A 1A2A1A0A0
Starting Byte
Address
A1A2A3A4A5A6A7 A
DS1077L
ACK
NP
Byte N StopMaster
NACK
D1D2D3D4D5D6 D0D7
Byte n
D1D2D3D4D5D6
SDA
SCL
D7 D0 A
Master
ACK
Byte (n+1)
D1D2D3D4D5D6D7 D0 A
Master
ACK
DS1077L
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COMMAND SET
Data and control information is read from and written to the DS1077L in the format shown in Figure 3. To
write to the DS1077L, the master will issue the slave address of the DS1077L and the R/ W bit will be set to
0. After receiving an acknowledge, the bus master provides a command protocol. After receiving this
protocol, the DS1077L will issue an acknowledge, and then the master can send data to the DS1077L. If the
DS1077L is to be read, the master must send the command protocol as before, and then issue a repeat
START condition and then the control byte again, this time with the R/ W bit set to one to allow reading of
the data from the DS1077L. The command set for the DS1077L is as follows:
Access DIV [01]
If R/ W = 0, this command writes to the DIV register. After issuing this command, the next data byte value
is to be written into the DIV register.
If R/
W = 1, the next data byte read is the value stored in the DIV register.
Access MUX [02]
If R/ W = 0, this command writes to the MUX register. After issuing this command, the next data byte value
is to be written into the MUX register.
If R/ W = 1, the next data byte read is the value stored in the MUX register.
Access BUS [0D]
If R/ W = 0, this command writes to the BUS register. After issuing this command, the next data byte value
is to be written into the BUS register.
If R/ W = 1, the next data byte read is the value stored in the BUS register.
Write E2 [3F]
If WC = 0, the EEPROM is automatically written to at the end of each command, this is a DEFAULT
condition. In this case the command WRITE E2 is not needed
If WC = 1, the EEPROM is written when the WRITE E2 command is issued. On receipt of the WRITE E2
command the contents of the BUS, DIV, and MUX registers are written into the EEPROM, thus locking in
the register settings.
EXCEPTION: The BUS, DIV, and MUX registers are always automatically written to EEPROM after a
write to the BUS register regardless of the value of the WC bit.
APPLICATION INFORMATION
Power-Supply Decoupling
To achieve best results, decouple the power supply with 0.01µF and 0.1µF high-quality, ceramic, surface-
mount capacitors as close as possible to V
CC
/GND of the device. Surface-mount components minimize lead
inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency
response for decoupling applications.
Current Consumption
The active supply current can be significantly reduced by disabling OUT0 when not required and setting its
prescaler to divide by 8. Likewise, bypassing OUT1’s divider (and using only the prescaler) also
significantly reduces the supply current.

DS1077LU-66+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Clock Generators & Support Products EconOscillator/Dvdr 66Mhz 118mil 2-Wire
Lifecycle:
New from this manufacturer.
Delivery:
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