DS1077L
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NOTES:
1) All voltages are referenced to ground.
2) 4.87kHz is obtained from a -40MHz standard part.
3) Output voltage swings may be impaired at high frequencies combined with high output loading.
4) After this period, the first clock pulse is generated.
5) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH
MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
6) The maximum t
HD:DAT
has only to be met if the device does not stretch the low period (t
LOW
) of the
SCL signal.
7) A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
>250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t
R MAX
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
8) C
B
— Total capacitance of one bus line in pF.
9) Jitter accumulates over N clock cycles as: (3 sigma jitter)(no. of cycles)
0.65
.
10) Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 3 preconditioning with
1000 temperature cycles of -55°C to +125°C, 336hr max V
CC
biased +125°C bake. Level 3
preconditioning consists of a 24hr +125°C storage bake, 192hr moisture soak at +30°C/60% R.H., and
three solder reflow passes.
TIMING DIAGRAM
SU:STO
t
t
SP
HD:STA
t
t
SU:STA
SU:DAT
t
t
HIGH
R
t
t
LOW
t
HD:STA
SCL
START
SDA
STOP
t
BUF
t
F
REPEATED
START
t
HD:DAT
ORDERING INFORMATION:
DS1077L Master Frequency (MHz)
40, 50, 60, 66.66
PACKAGE TYPE:
Z = SO (150MIL)
U = µSOP
