P3P623S00B, P3P623S00E
www.onsemi.com
2
Figure 1. General Block Diagram
PLL
CLKIN
VDD
DLY_CTRL
SS%
GND
SSON
CLKOUT(s)*
(Timing−Safe)
*For P3P623S00E − 8 CLKOUTS
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the edge
rates also get faster. Analysis shows that a square wave is
composed of fundamental frequency and harmonics. The
fundamental frequency and harmonics generate the energy
peaks that become the source of EMI. Regulatory agencies
test electronic equipment by measuring the amount of peak
energy radiated from the equipment. In fact, the peak level
allowed decreases as the frequency increases. The standard
methods of reducing EMI are to use shielding, filtering,
multi−layer PCBs, etc. These methods are expensive.
Spread spectrum clocking reduces the peak energy by
reducing the Q factor of the clock. This is done by slowly
modulating the clock frequency. The P3P623S00B/E uses
the center modulation spread spectrum technique in which
the modulated output frequency varies above and below the
reference frequency with a specified modulation rate. With
center modulation, the average frequency is the same as the
unmodulated frequency and there is no performance
degradation.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input−output delay.
For applications requiring zero input−output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero input−output
delay.
Timing−Safe Technology
Timing−Safe technology is the ability to modulate a clock
source with Spread Spectrum technology and maintain
synchronization with any associated data path.
Table 1. PIN DESCRIPTION FOR P3P623S00B
Pin # Pin Name Type Description
1 CLKIN (Note 1) Input External reference Clock input, 5 V tolerant input
2 NC No Connect
3 SS% (Note 3) Input Spread Spectrum Selection. Has an internal pull up resistor
4 GND Power Ground
5 SSON (Note 3) Input Spread Spectrum enable and disable option. When SSON is HIGH, the spread spectrum is
enabled and when LOW, it turns off the spread spectrum. Has an internal pull up resistor
6 CLKOUT (Note 2) Output Buffered clock output (Note 4)
7 VDD Power 3.3 V supply
8 NC No Connect
1. Weak pull down
2. Weak pull−down on all outputs
3. Weak pull−up on these inputs
4. Buffered clock output is Timing−Safe
