P3P623S00BG-08SR

P3P623S00B, P3P623S00E
www.onsemi.com
4
Table 5. OPERATING CONDITIONS
Parameter Description Min Max Unit
VDD Operating Voltage 3.0 3.6 V
T
A
Operating Temperature (Ambient Temperature) −40 +85 °C
C
L
Load Capacitance 30 pF
C
IN
Input Capacitance 7 pF
Table 6. ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions Min Typ Max Units
V
IL
Input Low Voltage (Note 5) 0.8 V
V
IH
Input High Voltage (Note 5) 2.0 V
I
IL
Input LOW Current V
IN
= 0 V 50
mA
I
IH
Input HIGH Current V
IN
= VDD 100
mA
V
OL
Output LOW Voltage (Note 6) I
OL
= 8 mA 0.4 V
V
OH
Output HIGH Voltage (Note 6) I
OH
= −8 mA 2.4 V
I
DD
Supply Current Unloaded outputs 27 mA
Z
O
Output Impedance 23
W
5. CLKIN input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Table 7. SWITCHING CHARACTERISTICS
Parameter Test Conditions Min Typ Max Units
Input Frequency 20 50 MHz
Output Frequency 30 pF load 20 50 MHz
Duty Cycle (Notes 7, 8) = (t
2
/ t
1
) x 100 Measured at VDD/2 40 50 60 %
Output Rise Time (Notes 7, 8) Measured between 0.8 V and 2.0 V 2.5 nS
Output Fall Time (Notes 7, 8) Measured between 2.0 V and 0.8 V 2.5 nS
Output−to−Output Skew (Notes 7, 8) All outputs equally loaded with SSOFF 250 pS
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge (Note 8)
Measured at VDD/2 with SSOFF ±350 pS
Device−to−Device Skew (Note 8) Measured at VDD/2 on the CLKOUT
pins of the device
700 pS
Cycle−to−Cycle Jitter (Notes 7, 8) Loaded outputs ±250 pS
PLL Lock Time (Note 8) Stable power supply, valid clock presen-
ted on CLKIN pin
1.0 mS
7. All parameters specified with 30 pF loaded outputs.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
P3P623S00B, P3P623S00E
www.onsemi.com
5
Switching Waveforms
Figure 2. Duty Cycle Timing
Figure 3. All Outputs Rise/Fall Time
Figure 4. Output−Output Skew
Figure 5. Input−Output Propagation Delay
Figure 6. Device−Device Skew
OUTPUT
OUTPUT
0.8 V
2 V
0.8 V
2 V
OUTPUT
OUTPUT
OUTPUT
INPUT
t
2
t
1
t
3
t
4
t
5
V
DD
/2
V
DD
/2
V
DD
/2 V
DD
/2 V
DD
/2
V
DD
/2
V
DD
/2
t
6
CLKOUT, Device 2
CLKOUT, Device 1
V
DD
/2
V
DD
/2
t
7
P3P623S00B, P3P623S00E
www.onsemi.com
6
Figure 7. Input−Output Skew
T
SKEW
One clock cycle
N=1
T
SKEW
+
T
SKEW
represents input−output skew
when spread spectrum is ON
Input clock 32 MHz, translates in to
(1/32 MHz)*0.125 = 3.90 nS
Timing−Safe
Output
Input
For example, T
SKEW
= ±0.125 for an
Figure 8. Test Circuit
V
DD
GND
LOAD
OUTPUT
0.1uF
+3.3V
0.1uF
+3.3V
V
DD
CLKOUT
Figure 9. Typical Example of Timing−Safe Waveform
Input
CLKOUT with SSOFF
Input
Timing−Safe CLKOUT

P3P623S00BG-08SR

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products 20-50M 3.3V 1 O/P TS EMI
Lifecycle:
New from this manufacturer.
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