MAX15038
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high imped-
ance when V
FB
is above 0.925 x V
REFIN
and V
REFIN
is
above 0.54V for at least 48 clock cycles. PWRGD pulls
low when V
FB
is below 90% of V
REFIN
or V
REFIN
is
below 0.54V for at least 48 clock cycles. PWRGD is low
when the IC is in shutdown mode, V
DD
is below the
internal UVLO threshold, or the IC is in thermal shut-
down mode.
Programming the Output Voltage
(CTL1, CTL2)
As shown in Table 1, the output voltage is pin program-
mable by the logic states of CTL1 and CTL2. CTL1 and
CTL2 are trilevel inputs: V
DD
, unconnected, and GND.
An 8.06kΩ resistor must be connected between V
OUT
and FB when CTL1 and CTL2 are connected to GND.
The logic states of CTL1 and CTL2 should be pro-
grammed only before power-up. Once the part is
enabled, CTL1 and CTL2 should not be changed. If the
output voltage needs to be reprogrammed, cycle
power or EN and reprogram before enabling. The out-
put voltage can be programmed continuously from
0.6V to 90% of V
IN
by using a resistor-divider network
from V
OUT
to FB to GND as shown in Figure 3a. CTL1
and CTL2 must be connected to GND.
Shutdown Mode
Drive EN to GND to shut down the IC and reduce quies-
cent current to a typical value of 10µA. During shutdown,
the LX is high impedance. Drive EN high to enable the
MAX15038.
Thermal Protection
Thermal-overload protection limits total power dissipation
in the device. When the junction temperature exceeds
T
J
= +165°C, a thermal sensor forces the device into
shutdown, allowing the die to cool. The thermal sensor
turns the device on again after the junction temperature
cools by 20°C, causing a pulsed output during continu-
ous overload conditions. The soft-start sequence begins
after recovery from a thermal-shutdown condition.
Applications Information
IN and V
DD
Decoupling
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of
the MAX15038, decouple IN with a 22µF capacitor from
IN to PGND. Also, decouple V
DD
with a 2.2µF
low-ESR ceramic capacitor from V
DD
to GND. Place
these capacitors as close as possible to the IC.
Inductor Selection
Choose an inductor with the following equation:
where LIR is the ratio of the inductor ripple current to full
load current at the minimum duty cycle. Choose LIR
between 20% to 40% for best performance and stability.
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron ferrite
core types are often the best choice for performance.
With any core material, the core must be large enough
not to saturate at the current limit of the MAX15038.
Output-Capacitor Selection
The key selection parameters for the output capacitor
are capacitance, ESR, ESL, and voltage-rating require-
ments. These affect the overall stability, output ripple
voltage, and transient response of the DC-DC convert-
er. The output ripple occurs due to variations in the
charge stored in the output capacitor, the voltage drop
due to the capacitor’s ESR, and the voltage drop due to
the capacitor’s ESL. Estimate the output-voltage ripple
due to the output capacitance, ESR, and ESL:
VV V V
RIPPLE RIPPLE C RIPPLE ESR RIPPLE ESL
=+ +
() ( ) ( ))
L
VVV
fV LIRI
OUT IN OUT
SIN OUTMAX
=
×−
×××
()
()
CTL1 CTL2 V
OUT
(V)
V
OUT
WHEN
USING
EXTERNAL
V
REFIN
(V)
GND GND
0.6* or
0.6 < V
OUT
0.9 x V
IN
**
V
REFIN
* or
V
REFIN
< V
OUT
0.9 x V
IN
**
V
DD
V
DD
0.7 V
REFIN
x (7/6)
GND Unconnected 0.8 V
REFIN
x (4/3)
GND V
DD
1.0 V
REFIN
x (5/3)
Unconnected GND 1.2 V
REFIN
x 2
Unconnected Unconnected 1.5 V
REFIN
x 2.5
Unconnected V
DD
1.8 V
REFIN
x 3
V
DD
GND 2.0 V
REFIN
x (10/3)
V
DD
Unconnected 2.5 V
REFIN
x (25/6)
Table 1. CTL1 and CTL2 Output Voltage
Selection
4A, 2MHz Step-Down Regulator
with Integrated Switches
______________________________________________________________________________________ 13
*
Install an 8.06k
Ω
resistor at R3 and do not install a resistor at R4.
**
Install R3 and R4 following the equation in the
Compensation
Design
section (see Figure 3a).
MAX15038
4A, 2MHz Step-Down Regulator
with Integrated Switches
14 ______________________________________________________________________________________
where the output ripple due to output capacitance,
ESR, and ESL is:
or:
or whichever is larger.
The peak-to-peak inductor current (I
P-P
) is:
Use these equations for initial output capacitor selec-
tion. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output-voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output-voltage rip-
ple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The ripple voltage due to
ESL is negligible when using ceramic capacitors.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
instantly changes by ESR x ΔI
LOAD
. Before the con-
troller can respond, the output deviates further,
depending on the inductor and output capacitor val-
ues. After a short time, the controller responds by regu-
lating the output voltage back to its predetermined
value. The controller response time depends on the
closed-loop bandwidth. A higher bandwidth yields a
faster response time, preventing the output from deviat-
ing further from its regulating value. See the
Compen-
sation Design
section for more details.
Input-Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the IC. The total input capacitance must be
equal or greater than the value given by the following
equation to keep the input-ripple voltage within
specification and minimize the high-frequency ripple
current being fed back to the input source:
where V
IN-RIPPLE
is the maximum allowed input ripple
voltage across the input capacitors and is recommended
to be less than 2% of the minimum input voltage. D is
the duty cycle (V
OUT
/V
IN
) and T
S
is the switching peri-
od (1/f
S
).
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor. The input capacitor must meet the ripple
current requirement imposed by the switching currents.
The RMS input ripple current is given by:
where I
RIPPLE
is the input RMS ripple current.
Compensation Design
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the
inductor L and the output capacitor C
O
. The ESR of the
output capacitor determines the zero. The double pole
and zero frequencies are given as follows:
where R
L
is equal to the sum of the output inductor’s DCR
(DC resistance) and the internal switch resistance,
R
DS(ON)
. A typical value for R
DS(ON)
is 24mΩ (low-side
MOSFET) and 31mΩ (high-side MOSFET). R
O
is the out-
put load resistance, which is equal to the rated output
voltage divided by the rated output current. ESR is the
total equivalent series resistance of the output capacitor.
If there is more than one output capacitor of the same
type in parallel, the value of the ESR in the above equa-
tion is equal to that of the ESR of a single output capacitor
divided by the total number of output capacitors.
The high switching frequency range of the MAX15038
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
quency of the associated transfer function zero is higher
than the unity-gain crossover frequency, f
C
, and the zero
cannot be used to compensate for the double pole creat-
ed by the output filtering inductor and capacitor. The dou-
ble pole produces a gain drop of 40dB/decade and a
phase shift of 180°. The compensation network error
f
x ESR x C
Z ESR
O
_
=
1
2π
ff
xLxC x
R ESR
RR
PLC P LC
O
O
OL
12
1
2
__
==
+
+
π
II
VVV
V
RIPPLE LOAD
OUT IN OUT
IN
×−()
C
DxT xI
V
IN MIN
SOUT
IN RIPPLE
_
=
I
VV
fL
x
V
V
PP
IN OUT
S
OUT
IN
=
×
V
I
t
x ESL
RIPPLE ESL
PP
OFF
()
=
V
I
t
x ESL
RIPPLE ESL
PP
ON
()
=
V I x ESR
RIPPLE ESR P P()
=
V
I
xC xf
RIPPLE C
PP
OUT S
()
=
8
MAX15038
amplifier must compensate for this gain drop and phase
shift to achieve a stable high-bandwidth closed-loop sys-
tem. Therefore, use type III compensation as shown in
Figures 3 and 4. Type III compensation possesses three
poles and two zeros with the first pole, f
P1_EA
, located at
zero frequency (DC). Locations of other poles and zeros
of the type III compensation are given by:
The above equations are based on the assumptions
that C1 >> C2 and R3 >> R2 are true in most applica-
tions. Placements of these poles and zeros are deter-
mined by the frequencies of the double pole and ESR
zero of the power transfer function. It is also a function
of the desired close-loop bandwidth. The following sec-
tion outlines the step-by-step design procedure to cal-
culate the required compensation components for the
MAX15038. When the output voltage of the MAX15038
is programmed to a preset voltage, R3 is internal to the
IC and R4 does not exist (Figure 3b).
When externally programming the MAX15038
(Figure 3a), the output voltage is determined by:
or:
if using an external V
REFIN
, and V
OUT
> V
REFIN
.
For a 0.6V output or for V
OUT
= V
REFIN
, connect an
8.06kΩ resistor from FB to V
OUT
. The zero-cross fre-
quency of the close-loop, f
C
, should be between 10%
and 20% of the switching frequency, f
S
. A higher zero-
cross frequency results in faster transient response.
Once f
C
is chosen, C1 is calculated from the following
equation:
where V
P-P
is the ramp peak-to-peak voltage (1V typ).
Due to the underdamped nature of the output LC double
pole, set the two zero frequencies of the type III compen-
sation less than the LC double-pole frequency to provide
adequate phase boost. Set the two zero frequencies to
80% of the LC double-pole frequency. Hence:
Setting the second compensation pole, f
P2_EA
, at
f
Z_ESR
yields:
C
xR
x
L x C x R ESR
RR
OO
LO
3
1
08 3
=
+
+.
()
R
xC
x
L x C x R ESR
RR
OO
LO
1
1
08 1
=
+
+.
()
C
V
V
fR
R
R
IN
PP
C
L
O
1
1 5625
231
=
×
×× × ×+
.
()π
R
V
RE
4 =
(
FFIN
OUT REFIN
R
V
×
()
3)
-V
R
R
V
for V V
OUT
OUT
4
06 3
06
06=
×
()
>
.
.
(.)
-
_
1
223
2
π
=
××
f
RC
PEA
f
PEA3 _
=
1
212π× ×RC
f
RC
ZEA2
1
233
_
=
××π
f
RC
ZEA1
1
211
_
=
××π
4A, 2MHz Step-Down Regulator
with Integrated Switches
______________________________________________________________________________________ 15
MAX15038
L
C
OUT
EXTERNAL RESISTIVE DIVIDER
INTERNAL PRESET VOLTAGES
V
OUT
R3
R4
R1
COMP
FB
OUT
CTL1
CTL2
LX
C1
C3
R2
C3
R2
C2
MAX15038
L
a)
b)
C
OUT
V
OUT
R3
8kΩ
R1
COMP
OUT
FB
CTL1
VOLTAGE
SELECT
CTL2
LX
C1
C2
Figure 3. Type III Compensation Network

MAX15038ETG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Voltage Regulators 4A 2MHz Step-Down w/Integrated Switch
Lifecycle:
New from this manufacturer.
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