NB6L239
http://onsemi.com
6
Table 7. DC CHARACTERISTICS, LVTTL/LVCMOS INPUTS (V
CC
= 2.375 V to 3.465 V, V
EE
= 0 V, T
A
= −40°C to +85°C)
Symbol
Characteristic Min Typ Max Unit
V
IH
Input HIGH Voltage (LVCMOS/LVTTL) 2.0 V
CC
V
V
IL
Input LOW Voltage (LVCMOS/LVTTL) V
EE
0.8 V
I
IH
Input HIGH Current −150 150
mA
I
IL
Input LOW Current −150 150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 8. AC CHARACTERISTICS V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V (Note 8)
Symbol
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
f
inMAX
Maximum Input CLOCK Frequency 3.0 3.0 3.0 GHz
V
OUTPP
Output Voltage Amplitude (Notes 10, 11)
QA(B2, 4, 8), QB(Bn) f
in
v 3.0 GHz
QA(B1), QB(Bn) f
in
v 2.5 GHz
QA(B1), QB(Bn) 2.5 GHz < f
in
v 3.0 GHz
450
450
300
650
650
650
450
450
250
650
630
650
450
450
200
650
610
650
mV
t
PLH
,
t
PHL
Propagation Delay to CLK, Qn
Output Differential @ 50 MHz MR
, Qn
370
330
470
370
570
430
370
330
470
380
570
430
400
330
500
400
600
480
ps
t
RR
Reset Recovery 0 −90 0 −90 0 −90 ps
t
s
Setup Time @ 50 MHz EN, CLK
SELA/B, CLK
0
0
−60
−300
0
0
−60
−300
0
0
−60
−300
ps
t
h
Hold Time @ 50 MHz CLK, EN
CLK, SELA/B
150
700
65
200
150
700
65
200
150
700
65
200
ps
t
skew
Within−Device Skew @ 50 MHz (Note 9)
Device−to−Device Skew (Note 9)
Duty Cycle Skew (Note 9)
5
25
25
30
80
40
5
30
30
30
90
45
6
30
30
35
90
45
ps
t
PW
Minimum Pulse Width MR 550 550 550 ps
t
JITTER
RMS Random Clock Jitter
(See Figure 20. F
max
/JITTER)
< 1 < 1 < 1 ps
V
INPP
Input Voltage Swing (Differential Configuration)
(Note 10)
100 V
CC
−V
EE
100 V
CC
−V
EE
100 V
CC
−V
EE
mV
t
r
t
f
Output Rise/Fall Times @ 50 MHz Qn, Qn
(20% − 80%)
30 60 120 30 65 120 30 70 120 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured using a 750 mV, 50% duty cycle clock source. All loading with 50 W to V
CC
− 2.0 V.
9. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation
when the delays are measured from the cross point of the inputs to the cross point of the outputs.
10.Input and output voltage swing is a single−ended measurement operating in differential mode.
11. Output Voltage Amplitude (V
OHCLK
− V
OLCLK
) at input CLOCK frequency, f
in
. The output frequency, f
out
, is the input CLOCK frequency
divided by n, f
out
= f
in
B n. Input CLOCK frequency is v3.0 GHz.
