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72V51253L7-5BB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
37
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
RADEN
Qout
REN
tAH
tAS
0001xx
RDADD
tA
NULL QUEUE
SELECT
*A*
*B* *C* *E* *F*
tQH
tENS
Q1 Wn-3 Q1 Wn-2 Q1 Wn-1
tA tA
Q1 Wn
tA
Q3 W0
FWFT
OV
tROV
tROV
5941 drw18
SELECT
NEW QUEUE
*D*
000011
t
AH
t
AS
t
QH
t
QS
t
ENH
t
QS
D0 Q3
Figure 16. Read Operation and Null Queue Select
NOTES:
1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words
from that queue.
2. Please see Figure 17, Null Queue Flow Diagram.
Cycle:
*A* Null-Q of device 0 is selected, when word Wn-1 from previously selected Q1 is read.
*B* REN is HIGH and Wn (Last Word of the Packet) of Q1 is pipelined onto the O/P register.
Note: *B* and *C* are a minimum 2 RCLK cycles between Q selects.
*C* The Null-Q is seen as an empty queue on the read side, therefore Wn of Q1 remains in the O/P register and OV goes HIGH.
*D* A new Q, Q3 is selected and the 1st word of Q3 will fall through present on the O/P register on cycle *F*.
5941 drw19
Queue 1
Memory
*A*
Null
Queue
*B*
Null
Queue
*C*
O/P Reg.
*D* *E* *F*
Null
Queue
Queue 3
Memory
Q1
Wn
Queue 3
Memory
O/P Reg. O/P Reg. O/P Reg. O/P Reg. O/P Reg.
Qn
Wn-1
Q1
Wn
Q1
Wn
Q1
Wn
Q1
Wn
Q1
Wn
Q1
Wn
Q3
W0
Q1
Wn
Q3
W1
Q3
W0
Figure 17. Null Queue Flow Diagram
38
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WCLK
WADEN
t
QH
t
QS
t
AH
t
AS
WRADD
D
1
Q
2
PAF
(Device 1)
t
AFLZ
5941 drw20
WEN
t
ENS
t
AH
t
AS
t
QH
t
QS
t
DH
t
DS
W
D-m
Din
t
WAF
t
WAF
HIGH-Z
t
ENH
D
1
Q
0
PAF
(Device 2)
t
FFHZ
12
D
1
Q
2
*B* *C* *E* *F*
*D*
*A*
Figure 18. Almost Full Flag Timing and Queue Switch
Figure 19. Almost Full Flag Timing
WCLK
WEN
PAF
RCLK
tWAF
REN
5941 drw21
D - (m+1) words in Queue D - m words in Queue
1
2
1
D-(m+1) words
in Queue
tWAF
tENHtENS
tSKEW2
tENHtENS
tCLKL
tCLKL
Cycle:
*A* Queue 2 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* Word, Wd-m is written into Q2 causing the PAF flag to go from HIGH to LOW. The flag latency is 2 WCLK cycles + tWAF.
*D* Queue 0 if device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 2 WCLK + tWAF latency.
*E* The PAF flag goes LOW based on the write 2 cycles earlier.
*F* The PAF flag goes HIGH due to the queue switch to Q0.
NOTE:
1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + tWAF
De-assertion: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there will be one extra WCLK cycle.
39
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 20. Almost Empty Flag Timing and Queue Switch
Figure 21. Almost Empty Flag Timing
RCLK
RADEN
t
QH
t
QS
t
AH
t
AS
RDADD
D1 Q3
PAE
(Device 1)
t
AELZ
5941 drw22
REN
t
AH
t
AS
t
QH
t
QS
t
OLZ
Qout
t
RAE
t
RAE
HIGH-Z
D1 Q1
PAE
(Device 2)
t
AEHZ
HIGH
HIGH-Z
t
A
D1 Q3 Wn
HIGH-Z
*B* *C* *E* *F**D**A*
t
A
D1 Q3 Wn+1
t
A
D1 Q1 W0
t
A
D1 Q1 W1
*G*
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAE
RCLK
t
ENS
n+1 words in Queue
t
RAE
t
SKEW2
t
RAE
12
REN
5941 drw23
t
ENS
t
ENH
n+2 words in Queue
n+1 words in Queue
Cycle:
*A* Queue 3 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* The PAE flag output now switches to device 1. Word, Wn is read from Q3 due to the FWFT operation. This read operation from Q3 is at the almost empty boundary, therefore
PAE will go LOW 2 RCLK cycles later.
*D* Q1 of device 1 is selected.
*E* The PAE flag goes LOW due to the read from Q3 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*F* Word, W0 is read from Q1 due to the FWFT operation. The PAE flag goes HIGH to show that Q1 is not almost empty.
NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + tRAE
De-assertion: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there will be one extra RCLK cycle.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

72V51253L7-5BB

Mfr. #:
Buy 72V51253L7-5BB
Manufacturer:
IDT
Description:
FIFO X18 4Q 2M MULTI-QUE
Lifecycle:
New from this manufacturer.
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