5
PRELIMINARY
AT91SAM7A2 - Summary
6021BS–ATARM–07/04
Signal Description
Table 2.
Signal Description
Module Name Function Type
Active
Level Comments
EBI
ADD[19:1] External address bus O (Z)
(1)
The EBI is tri-stated when NRESET is at a
logical low level.
Internal pull-downs on data bus bits
ADD0/NLB External address line line/
Lower byte enable
OL (Z)
ADD20/CS3 External address line/ Chip select O H (Z)
D[15:0] External data bus I/O (Z)
NOE Output enable O L (Z)
NWR0/NWE Write enable O L (Z)
NCS[2:0] Chip select lines O L (Z)
NWR1/NUB Upper byte enable O L (Z)
NWAIT External Wait I L Disable at reset, multiplexed with UPIO30
CORECLK Core CLock O Disable at reset, multiplexed with UPIO31
GIC
IRQ[1:0] External interrupt lines I
FIQ Fast interrupt line I
Power-on
Reset
NRESET Hardware reset input I L Schmitt input with internal filter
Master Clock
MCKI Master clock input I
Connected to external crystal (4 to 6 Mhz)
MCKO Master clock output O
PLLRC PLL RC network input I
32.768 kHz
clock
RTCKI 32.768 KHz clock input I Connected to external 32.768 Khz crystal
RTCKO 32.768 KHz clock output O
PIO UPIO[31:0] General purpose I/O I/O (Z)
USART0
SCK0/MPIO USART0 clock line I/O (Z) Multiplexed with general purpose I/O
RXD0/MPIO USART0 receive line I/O (Z) Multiplexed with general purpose I/O
TXD0/MPIO USART0 transmit line I/O (Z) Multiplexed with general purpose I/O
USART1
SCK1/MPIO USART1 clock line I/O (Z) Multiplexed with general purpose I/O
RXD1/MPIO USART1 receive line I/O (Z) Multiplexed with general purpose I/O
TXD1/MPIO USART1 transmit line I/O (Z) Multiplexed with general purpose I/O
Capture0 CAPT0 Capture input I
Capture1 CAPT1 Capture input I
PWM PWM[3:0] Pulse Width Modulation output O (L)
Timer T0
T0TIOA[2:0]/MPIO Capture/waveform I/O I/O (Z) Multiplexed with a general purpose I/O
T0TIOB[2:0]/MPIO Trigger/waveform I/O I/O (Z) Multiplexed with a general purpose I/O
T0TIOCLK[2:0]/MP
IO
External clock/trigger/input I/O (Z)
Multiplexed with a general purpose I/O
