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7024S35J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
6.42
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
Either condition must be valid for the entire t
EW time.
4. The specification for t
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH
and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
Symbol Parameter
7024X15
Com'l Only
7024X17
Com'l Only
7024X20
Com'l, Ind
& Military
7024X25
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 15
____
17
____
20
____
25
____
ns
t
EW
Chip Enable to End-of-Write
(3 )
12
____
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write 12
____
12
____
15
____
20
____
ns
t
AS
Address Set-up Time
(3 )
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
12
____
15
____
20
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
10
____
15
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10
____
12
____
15 ns
t
DH
Data Hold Time
(4 )
0
____
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
10
____
10
____
12
____
15 ns
t
OW
Output Active from End-of-Write
(1 , 2,4 )
0
____
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
5
____
ns
2740 tbl 13a
Symbol Parameter
7024X35
Com'l &
Military
7024X55
Com'l, Ind
& Military
7024X70
Military Only
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 35
____
55
____
70
____
ns
t
EW
Chip Enable to End-of-Write
(3 )
30
____
45
____
50
____
ns
t
AW
Address Valid to End-of-Write 30
____
45
____
50
____
ns
t
AS
Address Set-up Time
(3 )
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 25
____
40
____
50
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
30
____
40
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25
____
30 ns
t
DH
Data Hold Time
(4 )
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
25
____
30 ns
t
OW
Output Active from End-of-Write
(1 , 2, 4)
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
2740 tbl 13b
6.42
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
11
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing
(1,5)
NOTES:
1. R/W or CE or UB & LB = V
IH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a UB or LB = VIL and a CE = VIL and a R/W = VIL for memory array writing cycle.
3. t
WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH = VIL to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW = V
IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, UB, or LB.
7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured 0mV steady state with the Output Test Load
(Figure 2).
8. If OE = V
IL during R/W controlled write cycle, the write pulse width must be the larger of tWP for (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t
WP .
9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be
met for either condition.
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4) (4)
(7)
UB or LB
2740 drw 09
(9)
CE or SEM
(9)
(7)
(3)
2740 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
UB or LB
(3)
(2)
(6)
CE or SEM
(9)
(9)
6.42
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
12
Timing Waveform of Semaphore Read after Write Timing, Either Side
(1)
NOTES:
1. CE = V
IH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATA
OUT VALID” represents all I/O's (I/O0-I/O15) equal to the semaphore value.
NOTES:
1. D
0R = D0L = VIL, CER = CEL = VIH, or both UB & LB = VIH, semaphore flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W
A or SEMA going HIGH to R/WB or SEMB going HIGH.
4. If t
SPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
Timing Waveform of Semaphore Write Contention
(1,3,4)
SEM
2740 drw 11
t
AW
t
EW
t
SOP
I/O
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
Read CycleWrite Cycle
A
0
-A
2
OE
VALID
(2)
SEM
"A"
2740 drw 12
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE
"A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE
(2)
"B"
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

7024S35J

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Buy 7024S35J
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Description:
SRAM 4KX16 DUAL PORT STAT RAM
Lifecycle:
New from this manufacturer.
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