6.42
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
8
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL, UB or LB = VIL, and SEM =VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM =VIL.
4. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(4)
7024X15
Com'l Only
7024X17
Com'l Only
7024X20
Com'l, Ind
& Military
7024X25
Com'l &
Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 15
____
17
____
20
____
25
____
ns
t
AA
Address Access Time
____
15
____
17
____
20
____
25 ns
t
ACE
Chip Enable Access Time
(3 )
____
15
____
17
____
20
____
25 ns
t
ABE
Byte Enable Access Time
(3 )
____
15
____
17
____
20
____
25 ns
t
AOE
Output Enable Access Time
____
10
____
10
____
12
____
13 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10
____
12
____
15 ns
t
PU
Chip Enable to Power Up Time
(1,2)
0
____
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(1,2)
____
15
____
17
____
20
____
25 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
10
____
10
____
ns
t
SAA
Semaphore Address Access
(3 )
____
15
____
17
____
20
____
25 ns
2740 tbl 12a
7024X35
Com'l &
Military
7024X55
Com'l, Ind
& Military
7024X70
Military Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 35
____
55
____
70
____
ns
t
AA
Address Access Time
____
35
____
55
____
70 ns
t
ACE
Chip Enable Access Time
(3 )
____
35
____
55
____
70 ns
t
ABE
Byte Enable Access Time
(3 )
____
35
____
55
____
70 ns
t
AOE
Output Enable Access Time
____
20
____
30
____
35 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25
____
30 ns
t
PU
Chip Enable to Power Up Time
(1,2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(1,2)
____
35
____
50
____
50 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)15
____
15
____
15
____
ns
t
SAA
Semaphore Address Access
(3)
____
35
____
55
____
70 ns
2740 tbl 12b
