SP6660DS/11 SP6660 200mA Charge Pump Inverter or Doubler © Copyright 2000 Sipex Corporation
13
For a nominal f
PUMP
of 5kHz (where f
OSC
=10kHz)
and C2=150µF with an ESR of 0.2, the ripple
is approximately 90mV with a 100mA load
current. If C2 is raised to 390µF, the ripple drops
to 45mV. The output ripple voltage is calculated
by noting that capacitor C2 supplies the output
current during one-half of the charge pump cycle.
OSC is internally connected to a 15pF capacitor.
An external capacitor can be added to slow the
oscillator. Designers should take care to
minimize stray capacitance. An external
oscillator may also be connected to overdrive
OSC. Refer to the Oscillator Control section
for further details.
Figure 22. Typical Operating Circuit for the Positive Voltage Doubler
OSC
OUT
SP6660
+V
IN
+1.5V to +4.25V
C1
1µF to 150µF
5
1
2
7
4
FC
C2
1µF to 150µF
CAP+
CAP-
GND
6
8
3
LV
DOUBLE
VOLTAGE
OUTPUT
TYPICAL CIRCUIT: VOLTAGE DOUBLER
+V
Positive Voltage Doubler
The SP6660 can double the output voltage of an
input power supply or battery. From a +4.25V
input, the circuit in Figure 22 can provide 100mA
with +8.0V at V+. The no-load voltage output at
V+ is 2(V
INL
).
LV may be tied to OUT pin for all input voltages
in the positive voltage doubler mode. Connect
the power-supply positive voltage input to GND
pin. Connect the power-supply ground input to
OUT pin. V+ is the positive voltage output in
this mode.
Designers may overdrive OSC in the positive
voltage doubler mode. Refer to the Oscillator
Control section for further details.
SP6660DS/11 SP6660 200mA Charge Pump Inverter or Doubler © Copyright 2000 Sipex Corporation
14
Oscillator Control
Refer to Figure 23 for a table of the four control
modes of the SP6660 internal oscillator
frequencies. In the first mode, FC and OSC are
open (unconnected) and the internal oscillator
typically runs at 10kHz. OSC is internally
connected to a 15pF capacitor.
In the second mode, FC is connected to V+. The
charge and discharge current at OSC changes
from 1.0µA to 8.0µA, increasing the oscillator
frequency eight times to 80kHz.
In the third mode, the oscillator frequency is
lowered by connecting a capacitor between OSC
and GND. FC can still multiply the frequency
by eight times in this mode, but for a lower range
of frequencies. Refer to Figure 11 for these ranges.
In the fourth mode, any standard CMOS logic
output can be used to drive OSC. OSC may be
overdriven by an external oscillator that swings
between V
IN
and GND. When OSC is overdriven,
FC has no effect.
Unlike the 7660 and 660 industry standards,
designers may overdrive the oscillator of the
SP6660 in both the inverting and the Voltage
Doubling Mode.
Figure 23. Four control modes for the SP6660
Oscillator Frequency
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Optimizing Loss Conditions
Losses in SP6660 applications can be anticipated
from the following:
1. Output Resistance:
V
LOSS
= I
LOAD
x R
OUT
where V
LOSS
is the voltage drop due to the
SP6660 output resistance, I
LOAD
is the load
current, and R
OUT
is the SP6660 output resistance.
2. Charge Pump Capacitor ESR:
V
LOSSC1
4 x ESR
C1
x I
LOAD
where V
LOSSC1
is the voltage drop due to the
charge pump capacitor, C1, ESR
C1
is the ESR of
C1, and I
LOAD
is the load current. The loss in C1
is larger than the loss in the reservoir capacitor,
C2, because it handles a current almost four
times larger than the load current during charge-
pump operation. As a result of this, a change in
the capacitor ESR has a much greater impact on
the performance of the SP6660 for C1 than for C2.
3. Reservoir Capacitor ESR:
V
LOSSC2
= ESR
C2
x I
LOAD
where V
LOSSC2
is the voltage drop due to the
reservoir capacitor C2, ESR
C2
is the ESR of C2,
and I
LOAD
is the load current. Increasing the
capacitance of C2 and/or reducing its ESR
can reduce the output ripple that may be
caused by the charge pump. A designer can
filter high-frequency noise at the output
by implementing a low ESR capacitor at C2.
Generally, capacitors with larger capacitance
values and higher voltage ratings tend to
reduce ESR.
SP6660DS/11 SP6660 200mA Charge Pump Inverter or Doubler © Copyright 2000 Sipex Corporation
15
Optimizing Capacitor Selection
Refer to Figure 24 for the total output resistance
for various capacitance values and oscillator
frequencies. The reservoir and charge pump
capacitor values are equal. The capacitance
values required to maintain comparable ripple
and output resistance typically diminish
proportionately as the pump frequency of the
SP6660 increases.
The test conditions for the curves of Figure 24
are the same as for Figures 2 to 20 for the circuits
in Figures 1 and 2; additional conditions are as
follows:
C1 = C2 = 0.2 ESR capacitors
R
OUT
= 4.2
The flat portion of the curves shown at a 5.2
effective output resistance is a result of the
SP6660's 5.25 output resistance where
5.2 = R
OUT(SP6660)
+ (4 x ESR
C1
) + ESR
C2
.
Instead of the typical 5.2, R
OUT
= 4.2 is used
because the typical specification includes the
effect of the ESRs of the capacitors used in the
test circuit in Figures 1 and 2.
Refer to Figures 17, 18, 19 and 20 for the output
currents using 0.33µF to 220µF capacitors.
Output currents are plotted for 3.0V and 4.5V
inputs taking into consideration a 10% to 20%
loss in the input voltage. The SP6660 5.2
series resistance limits increases in output current
vs. capacitance for values much higher than
47µF. Larger values may still be useful to reduce
ripple.
Designing a Multiple of the SP6660
Negative Inverted Output Voltage
The SP6660 can be cascaded to allow a designer
to provide a multiple of the negative inverted
output voltage of a single SP6660 device. The
approximate total output resistance, R
TOT
,of the
cascaded SP6660 devices is equal to the sum of
the individual SP6660 output resistance values,
R
OUT
. The output voltage, V
TOT
, is a multiple of
the number of cascaded SP6660 devices and the
output voltage of an individual SP6660 device,
V
OUT
. Refer to Figure 25 for the circuit cascading
SP6660 devices. Note that the capacitance value
of C1 for the charge pump and C2 at V
OUT
is
multiplied respectively to the number of cascaded
SP6660 devices.
Connecting the SP6660 in Parallel
SP6660 devices can be connected in parallel
to reduce the total output resistance. The
approximate total output resistance, R
TOT
, of the
multiple devices connected in parallel is equal
to the output resistance of an individual SP6660
device divided by the total number of devices
connected. Refer to Figure 26 for the circuit
connecting multiple SP6660 devices in parallel.
Note that only the charge pump capacitor value
of C1 is multiplied respectively by the number
of SP6660 connected in parallel. A single
capacitor C2 at the output voltage V
OUT
of the
"nth" device connected in parallel serves all
devices connected.

SP6660EN-L/TR

Mfr. #:
Manufacturer:
MaxLinear
Description:
Switching Voltage Regulators 200mA Inverter or Doubler
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