One-PLL General-Purpose Flash-Programmable
and 2-Wire Serially Programmable Clock Generato
r
CY22150
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600
Document #: 38-07104 Rev. *F Revised August 11, 2004
Features
Integrated phase-locked loop (PLL)
Commercial and industrial operation
Flash-programmable
Field-programmable
2-wire serial programming interface
Low-skew, low-jitter, high-accuracy outputs
3.3V operation with 2.5V output option
16-lead TSSOP
Benefits
Internal PLL to generate six outputs up to 200 MHz. Able
to generate custom frequencies from an external
crystal or a driven source.
Performance guaranteed for applications that require
an extended temperature range.
Nonvolatile reprogrammable technology allows easy
customization, quick turnaround on design changes
and product performance enhancements, and better
inventory control. Parts can be reprogrammed up to 100
times, reducing inventory of custom parts and
providing an easy method for upgrading existing
designs.
The CY22150 can be programmed at the package level.
In-house programming of samples and prototype
quantities is available using the CY3672 FTG Devel-
opment Kit. Production quantities are available through
Cypress’s value-added distribution partners or by
using third party programmers from BP Micro-
systems, HiLo Systems, and others.
The CY22150 provides an industry-standard interface
for volatile, system-level customization of unique
frequencies and options. Serial programming and
reprogramming allows quick design changes and
product enhancements, eliminates inventory of old
design parts, and simplifies manufacturing.
High performance suited for commercial, industrial,
networking, telecomm and other general-purpose
applications.
Application compatibility in standard and low-power
systems.
Industry-standard packaging saves on board space.
Logic Block Diagram
SPI
Control
VDDL
AVDD
VSS
AVSS
SDAT
SCLK
Serial
VSSL
VDD
XIN
XOUT
LCLK1
Divider
PLL
OSC.
LCLK3
Q
P
VCO
Φ
LCLK2
LCKL4
CLK5
CLK6
Bank 1
Divider
Bank 2
Crosspoint
Switch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
SCLK
LCLK1
XIN
XOUT
VDD
SDAT
AVSS
LCLK3
LCLK2
CLK6
CLK5
AVDD
VDDL
LCLK4
Pin Configuration
Programming
Interface
Matrix
CY22150
Document #: 38-07104 Rev. *F Page 2 of 13
Frequency Calculation and Register Definitions
The CY22150 is an extremely flexible clock generator with four
basic variables that can be used to determine the final output
frequency. They are the input reference frequency (REF), the
internally calculated P and Q dividers, and the post divider,
which can be a fixed or calculated value. There are three basic
formulas for determining the final output frequency of a
CY22150-based design:
CLK = ((REF * P)/Q)/Post Divider
CLK = REF/Post Divider
•CLK = REF.
The basic PLL block diagram is shown in Figure 1. Each of the
six clock outputs on the CY22150 has a total of seven output
options available to it. There are six post divider options
available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N
and DIV2N are independently calculated and are applied to
individual output groups. The post divider options can be
applied to the calculated VCO frequency ((REF*P)/Q) or to the
REF directly.
In addition to the six post divider output options, the seventh
option bypasses the PLL and passes the REF directly to the
crosspoint switch matrix.
Note:
1. Float XOUT if XIN is driven by an external clock source.
Part Number Outputs Input Frequency Range Output Frequency Range Specifications
CY22150FC 6 8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
80 kHz–200 MHz (3.3V)
80 KHz–166.6 MHz (2.5V)
Field programmable
Serially programmable
Commercial temperature
CY22150FI 6 8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
80 kHz – 166.6 MHz (3.3V)
80 KHz – 150 MHz (2.5V)
Field programmable
Serially programmable
Industrial temperature
Pin Definitions
Pin Name Pin Number Pin Description
XIN 1 Reference Input. Driven by a crystal (8 MHz – 30 MHz) or external clock (1 MHz – 133 MHz).
Programmable input load capacitors allow for maximum flexibility in selecting a crystal,
regardless of manufacturer, process, performance, or quality.
VDD 2 3.3V voltage supply
AVDD 3 3.3V analog voltage supply
SDAT 4 Serial data input
AVSS 5 Analog ground
VSSL 6 LCLK ground
LCLK1 7 Configurable clock output 1 at V
DDL
level (3.3V or 2.5V)
LCLK2 8 Configurable clock output 2 at V
DDL
level (3.3V or 2.5V)
LCLK3 9 Configurable clock output 3 at V
DDL
level (3.3V or 2.5V)
SCLK 10 Serial clock input
VDDL 11 LCLK voltage supply (2.5V or 3.3V)
LCLK4 12 Configurable clock output 4 at V
DDL
level (3.3V or 2.5V)
VSS 13 Ground
CLK5 14 Configurable clock output 5 (3.3V)
CLK6 15 Configurable clock output 6 (3.3V)
XOUT
[1]
16 Reference output
CY22150
Document #: 38-07104 Rev. *F Page 3 of 13
Default Start-up Condition for the CY22150
The default (programmed) condition of the device is generally
set by the distributor who programs the device using a
customer-specific JEDEC file produced by CyClocksRT.
Parts shipped from the factory are blank and unprogrammed.
In this condition, all bits are set to 0, all outputs are
three-stated, and the crystal oscillator circuit is active.
While you can develop your own subroutine to program any or
all of the individual registers described in the following pages,
it may be easier to use CyClocksRT to produce the required
register setting file.
The serial interface address of the CY22150 is 69H. Should
there be a conflict with any other devices in your system, this
can also be changed using CyClocksRT.
Frequency Calculations and Register Defini-
tions Using the Serial Programming Interface
The CY22150 provides an industry standard serial interface
for volatile, in-system programming of unique frequencies and
options. Serial programming and reprogramming allows for
quick design changes and product enhancements, eliminates
inventory of old design parts, and simplifies manufacturing.
The Serial Programming Interface (SPI) provides volatile
programming, i.e., when the target system is powered down,
the CY22150 reverts to its pre-SPI state, as defined above
(programmed or unprogrammed). When the system is
powered back up again, the SPI registers will need to be
reconfigured again.
All programmable registers in the CY22150 are addressed
with eight bits and contain eight bits of data. The CY22150 is
a slave device with an address of 1101001 (69H).
Table 1 lists the SPI registers and their definitions. Specific
register definitions and their allowable values are listed below.
Reference Frequency
The REF can be a crystal or a driven frequency. For crystals,
the frequency range must be between 8 MHz and 30 MHz. For
a driven frequency, the frequency range must be between
1 MHz and 133 MHz.
Using a Crystal as the Reference Input
The input crystal oscillator of the CY22150 is an important
feature because of the flexibility it allows the user in selecting
a crystal as a REF source. The input oscillator has program-
mable gain, allowing for maximum compatibility with a
reference crystal, regardless of manufacturer, process, perfor-
mance and quality.
Programmable Crystal Input Oscillator Gain Settings
The Input crystal oscillator gain (XDRV) is controlled by two
bits in register 12H, and are set according to Table 2. The
parameters controlling the gain are the crystal frequency, the
internal crystal parasitic resistance (ESR, available from the
(Q+2)
VCO
(2(PB+4)+PO)
/2
/3
/2
LCLK1
LCLK2
LCLK3
LCLK4
CLK5
CLK6
CLKSRC
Crosspoint
Switch Matrix
[44H]
[44H]
[44H,45H]
[45H]
[45H,46H]
DIV2CLK
REF
PFD
Divider Bank 1
[45H]
DIV1SRC [OCH]
/4
DIV2SRC [47H]
Divider Bank 2
DIV1N [OCH]
DIV2N [47H]
DIV1CLK
/DIV1N
1
0
1
0
[42H]
[40H], [41H], [42H]
/DIV2N
Qtotal
Ptotal
CLKOE [09H]
Figure 1. Basic Block Diagram of CY22150 PLL

CY22150KFI

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL Flash/2-wire Clk Gen 1MHz-133MHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet