CY22150
Document #: 38-07104 Rev. *F Page 7 of 13
Programmable Interface Timing
The CY22150 utilizes a 2-wire serial-interface SDAT and
SCLK that operates up to 400 kbits/second in Read or Write
mode. The basic Write serial format is as follows.
Start Bit; seven-bit Device Address (DA); R/W
Bit; Slave Clock
Acknowledge (ACK); eight-bit Memory Address (MA); ACK;
eight-bit data; ACK; eight-bit data in MA + 1 if desired; ACK;
eight-bit data in MA+2; ACK; etc. until STOP bit.The basic
serial format is illustrated in Figure 3.
Data Valid
Data is valid when the Clock is HIGH, and may only be transi-
tioned when the clock is LOW, as illustrated in Figure 2.
Data Frame
Every new data frame is indicated by a start and stop
sequence, as illustrated in Figure 4.
Start Sequence – Start frame is indicated by SDAT going
LOW when SCLK is HIGH. Every time a Start signal is given,
the next eight-bit data must be the device address (seven bits)
and a R/W
bit, followed by register address (eight bits) and
register data (eight bits).
Stop Sequence – Stop frame is indicated by SDAT going
HIGH when SCLK is HIGH. A Stop frame frees the bus for
writing to another part on the same bus or writing to another
random register address.
Acknowledge Pulse
During Write mode, the CY22150 will respond with an ACK
pulse after every eight bits. This is accomplished by pulling the
SDAT line LOW during the N*9
th
clock cycle, as illustrated in
Figure 5. (N = the number of eight-bit segments transmitted.)
During Read mode, the ACK pulse after the data packet is sent
is generated by the master.
Table 11.
CLKSRC2 CLKSRC1 CLKSRC0 Definition and Notes
0 0 0 Reference input.
0 0 1 DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are
4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8.
0 1 0 DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.
0 1 1 DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.
1 0 0 DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are
4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8.
1 0 1 DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.
1 1 0 DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.
1 1 1 Reserved – do not use.
Table 12.
AddressD7D6D5D4D3D2D1D0
44H CLKSRC2
for LCLK1
CLKSRC1
for LCLK1
CLKSRC0
for LCLK1
CLKSRC2
for LCLK2
CLKSRC1
for LCLK2
CLKSRC0
for LCLK2
CLKSRC2
for LCLK3
CLKSRC1
for LCLK3
45H CLKSRC0
for LCLK3
CLKSRC2
for LCLK4
CLKSRC1
for LCLK4
CLKSRC0
for LCLK4
CLKSRC2
for CLK5
CLKSRC1
for CLK5
CLKSRC0
for CLK5
CLKSRC2
for CLK6
46H CLKSRC1
for CLK6
CLKSRC0
for CLK6
111111
Table 13. CLKOE Bit Setting
Address D7 D6 D5 D4 D3 D2 D1 D0
09H 0 0 CLK6 CLK5 LCLK4 LCLK3 LCLK2 LCLK1
Figure 2. Data Valid and Data Transition Periods
SDAT
SCLK
Data valid
Transition to next bit
CLK
LOW
CLK
HIGH
V
IH
V
IL
t
SU
t
DH
