GTL2107_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 23 December 2009 5 of 19
NXP Semiconductors
GTL2107
12-bit GTL−/GTL/GTL+ to LVTTL translator
[1] The enable on 7BO1/7BO2 includes a delay that prevents the transient condition (where 5BI/6BI goes from
LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns) from causing a low glitch on the
7BO1/7BO2 outputs.
[2] Open-drain input/output terminal is driven to logic LOW state by an external driver.
[1] Open-drain input/output terminal is driven to logic LOW state by an external driver.
Table 7. CPU SMI_L control
H = HIGH voltage level; L = LOW voltage level.
Inputs Output
10AI1/10AI2 9BI 10BO1/10BO2
LLL
LHL
HLL
HHH
Table 8. PROCHOT L control
H = HIGH voltage level; L = LOW voltage level.
Inputs Input/output Output
EN2 5BI/6BI 5A/6A (open-drain) 7BO1/7BO2
HLL H
[1]
HHL
[2]
L
HHH H
LHL
[2]
L
LHH H
LLH H
LLL
[2]
H
Table 9. Southbridge NMI control
H = HIGH voltage level; L = LOW voltage level.
Input Input/output Output
11BI 11A (open-drain) 11BO
LHL
LL
[1]
H
HLH
