Philips Semiconductors Product data
80C552/83C552
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
2002 Sep 03
13
AC ELECTRICAL CHARACTERISTICS
1,
2
16 MHz version
16 MHz CLOCK VARIABLE CLOCK
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT
1/t
CLCL
2 Oscillator frequency 3.5 16 MHz
t
LHLL
2 ALE pulse width 85 2t
CLCL
–40 ns
t
AVLL
2 Address valid to ALE low 8 t
CLCL
–55 ns
t
LLAX
2 Address hold after ALE low 28 t
CLCL
–35 ns
t
LLIV
2 ALE low to valid instruction in 150 4t
CLCL
–100 ns
t
LLPL
2 ALE low to PSEN low 23 t
CLCL
–40 ns
t
PLPH
2 PSEN pulse width 143 3t
CLCL
–45 ns
t
PLIV
2 PSEN low to valid instruction in 83 3t
CLCL
–105 ns
t
PXIX
2 Input instruction hold after PSEN 0 0 ns
t
PXIZ
2 Input instruction float after PSEN 38 t
CLCL
–25 ns
t
AVIV
2 Address to valid instruction in 208 5t
CLCL
–105 ns
t
PLAZ
2 PSEN low to address float 10 10 ns
Data Memory
t
RLRH
3 RD pulse width 275 6t
CLCL
–100 ns
t
WLWH
4 WR pulse width 275 6t
CLCL
–100 ns
t
RLDV
3 RD low to valid data in 148 5t
CLCL
–165 ns
t
RHDX
3 Data hold after RD 0 0 ns
t
RHDZ
3 Data float after RD 55 2t
CLCL
–70 ns
t
LLDV
3 ALE low to valid data in 350 8t
CLCL
–150 ns
t
AVDV
3 Address to valid data in 398 9t
CLCL
–165 ns
t
LLWL
3, 4 ALE low to RD or WR low 138 238 3t
CLCL
–50 3t
CLCL
+50 ns
t
AVWL
3, 4 Address valid to WR low or RD low 120 4t
CLCL
–130 ns
t
QVWX
4 Data valid to WR transition 3 t
CLCL
–60 ns
t
DW
4 Data before WR 288 7t
CLCL
–150 ns
t
WHQX
4 Data hold after WR 13 t
CLCL
–50 ns
t
RLAZ
3 RD low to address float 0 0 ns
t
WHLH
3, 4 RD or WR high to ALE high 23 103 t
CLCL
–40 t
CLCL
+40 ns
External Clock
t
CHCX
5 High time
4
20 20 ns
t
CLCX
5 Low time
4
20 20 ns
t
CLCH
5 Rise time
4
20 20 ns
t
CHCL
5 Fall time
4
20 20 ns
Serial Timing – Shift Register Mode
4
(Test Conditions: T
amb
= 0 °C to +70 °C; V
SS
= 0 V; Load Capacitance = 80 pF)
t
XLXL
6 Serial port clock cycle time 0.75 12t
CLCL
µs
t
QVXH
6 Output data setup to clock rising edge 492 10t
CLCL
–133 ns
t
XHQX
6 Output data hold after clock rising edge 8 2t
CLCL
–117 ns
t
XHDX
6 Input data hold after clock rising edge 0 0 ns
t
XHDV
6 Clock rising edge to input data valid 492 10t
CLCL
–133 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN
= 100 pF, load capacitance for all other outputs = 80 pF.
3. t
CLCL
= 1/f
OSC
= one oscillator clock period.
t
CLCL
= 83.3ns at f
OSC
= 12 MHz.
t
CLCL
= 62.5ns at f
OSC
= 16 MHz.
4. These values are characterized but not 100% production tested.
