Philips Semiconductors Product data
80C552/83C552
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
2002 Sep 03
16
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A Address
C Clock
D Input data
H Logic level high
I Instruction (program memory contents)
L Logic level low, or ALE
P PSEN
Q Output data
R–RD
signal
t Time
V Valid
W– WR
signal
X No longer a valid logic level
Z Float
Examples: t
AVLL
= Time for address valid to
ALE low.
t
LLPL
= Time for ALE low to
PSEN
low.
SU01694
t
PXIZ
ALE
PSEN
PORT 0
PORT 2
A8–A15 A8–A15
A0–A7 A0–A7
t
AVLL
t
PXIX
t
LLAX
INSTR IN
t
PLIV
t
LHLL
t
PLPH
t
LLIV
t
PLAZ
t
LLPL
t
AVIV
Figure 2. External Program Memory Read Cycle
SU01695
ALE
PSEN
PORT 0
PORT 2
RD
A0–A7
FROM RI OR DPL
DATA IN A0–A7 FROM PCL INSTR IN
P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH
t
WHLH
t
LLDV
t
LLWL
t
RLRH
t
LLAX
t
RLAZ
t
AVLL
t
RHDX
t
RHDZ
t
AVWL
t
AVDV
t
RLDV
Figure 3. External Data Memory Read Cycle
Philips Semiconductors Product data
80C552/83C552
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
2002 Sep 03
17
SU01696
t
LLAX
ALE
PSEN
PORT 0
PORT 2
WR
A0–A7
FROM RI OR DPL
DATA OUT A0–A7 FROM PCL INSTR IN
P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH
t
WHLH
t
LLWL
t
WLWH
t
AVLL
t
AVWL
t
QVWX
t
WHQX
t
DW
Figure 4. External Data Memory Write Cycle
SU01697
0.8 V
t
LOW
t
HIGH
V
IH1
V
IH1
0.8 V
t
CLCL
t
r
t
f
V
IH1
V
IH1
0.8 V 0.8 V
Figure 5. External Clock Drive XTAL1
SU01678
012345678
INSTRUCTION
ALE
CLOCK
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
CLEAR RI
VALID VALID VALID VALID VALID VALID VALID VALID
SET TI
SET RI
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
01234567
Figure 6. Shift Register Mode Timing
Philips Semiconductors Product data
80C552/83C552
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
2002 Sep 03
18
SU01699
V
DD
–0.5
0.45 V
0.2 V
DD
+0.9
0.2 V
DD
–0.1
NOTE:
AC INPUTS DURING TESTING ARE DRIVEN AT V
DD
–0.5 FOR A LOGIC ‘1’ AND
0.45 V FOR A LOGIC ‘0’. TIMING MEASUREMENTS ARE MADE AT V
IH
MIN FOR A
LOGIC ‘1’ AND V
IL
MAX FOR A LOGIC ‘0’.
Figure 7. AC Testing Input/Output
SU01700
V
LOAD
V
LOAD
+0.1 V
V
LOAD
–0.1 V
V
OH
–0.1 V
V
OL
+0.1 V
NOTE:
FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV
CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A
100 mV CHANGE FROM THE LOADED V
OH
/V
OL
LEVEL OCCURS. I
OH
/I
OL
> +
20mA.
TIMING
REFERENCE
POINTS
Figure 8. Float Waveform
SU01701
t
RD
t
SU;STA
t
BUF
t
SU;STO
0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
t
FD
t
RC
t
FC
t
HIGH
t
LOW
t
HD;STA
t
SU;DAT1
t
HD;DAT
t
SU;DAT2
t
SU;DAT3
START condition
repeated START condition
SDA
(INPUT/OUTPUT)
SCL
(INPUT/OUTPUT)
STOP condition
START or repeated START condition
Figure 9. Timing SIO1 (I
2
C) Interface

P80C552IBA/08,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT ROMLESS 68PLCC
Lifecycle:
New from this manufacturer.
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