7
LTC4006
4006fa
BLOCK DIAGRA
W
+
5
9k
1.19V
11.67µA
35mV
C/10
T
BAD
EA
g
m
= 1m
g
m
= 1m
1.19V
GND
13
TGATE
BGATE
Q1
Q2
11
CLP
100mV
15nF
20µF
R
CL
5.1k
12
CLN
15
PGND
L1
397mV
CHG
25µA
V
LOGIC
R
T
NTC
0.47µF
10k
NTC
R
RT
+
+
CL1
g
m
= 1.5m
TIMER/CONTROLLER
THERMISTOR
OSCILLATOR
2
4
6
BAT
3k
R
SENSE
CSP
I
TH
7
32.4k
100k
WATCH DOG
DETECT t
OFF
DCIN
OV
OSCILLATOR
1.28V
PWM
LOGIC
S
R
Q
CHARGE
I
REV
+
I
CMP
+
÷ 5
BUFFERED I
TH
14
0.1µF
I
MON
4006 BD
4.7nF
R
IMON1
26.44k
R
IMON2
52.87k
17mV
8
ACP/SHDN
3
INFET
Q3
DCIN
V
IN
16
1
+
I
CL
5.8V
CLN
3k
20µF
6.04k
0.12µF
CA2
+
CA1
10
9
+
RESTART
LOBAT
1.105V
708mV
8
LTC4006
4006fa
Overview
The LTC4006 is a synchronous current mode PWM step-
down (buck) switcher battery charger controller. The charge
current is programmed by the sense resistor (R
SENSE
)
between the CSP and BAT pins. The final float voltage is
internally programmed to 8.4V (LTC4006-6), 12.6V
(LTC4006-2) or 16.8V (LTC4006-4) with better than ±0.8%
accuracy. Charging begins when the potential at the DCIN
pin rises above the voltage at CLN (and the UVLO voltage)
and the ACP/SHDN pin is allowed to go high; the CHG pin
is set low. At the beginning of the charge cycle, if the cell
voltage is below 2.5V, the charger will trickle charge the
battery with 10% of the maximum programmed current.
If the cell voltage stays below 2.5V for 25% of the total
charge time, the charge sequence will be terminated im-
mediately and the CHG pin will be set to a high impedance.
An external thermistor network is sampled at regular
intervals. If the thermistor value exceeds design limits,
charging is suspended. If the thermistor value returns to
an acceptable value, charging resumes. An external resis-
tor on the R
T
pin sets the total charge time. The timer can
be defeated by forcing the CHG pin to a low voltage.
As the battery approaches the final float voltage, the charge
current will begin to decrease. When the current drops to
10% of the programmed charge current, an internal C/10
comparator will indicate this condition by sinking 25µA at the
CHG pin. The charge timer is also reset to 25% of the total
charge time. If this condition is caused by an input current
limit condition, described below, then the C/10 comparator
will be inhibited. When a time-out occurs, charging is termi-
nated immediately and the CHG pin changes to a high
impedance. The charger will automatically restart if the cell
voltage is less than 3.9V. To restart the charge cycle manu-
ally, simply remove the input voltage and reapply it, or force
the ACP/SHDN pin low momentarily. When the input voltage
is not present, the charger goes into a sleep mode, dropping
battery current drain to 15µA. This greatly reduces the current
drain on the battery and increases the standby time. The
charger can be inhibited at any time by forcing the ACP/SHDN
pin to a low voltage.
Input FET
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLN pin
and provides the logic indicator of AC present on the
ACP/SHDN pin. It controls the gate of the input FET to keep
a low forward voltage drop when charging and also
prevents reverse current flow through the input FET.
If the input voltage is less than V
CLN
, it must go at least
170mV higher than V
CLN
to activate the charger. When this
occurs the ACP/SHDN pin is released and pulled up with
an internal load to indicate that the adapter is present. The
gate of the input FET is driven to a voltage sufficient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLN drops to less than 25mV,
the input FET is turned off slowly. If the voltage between
DCIN and CLN is ever less than –25mV, then the input FET
is turned off in less than 10µs to prevent significant
reverse current from flowing in the input FET. In this
condition, the ACP/SHDN pin is driven low and the charger
is disabled.
Battery Charger Controller
The LTC4006 charger controller uses a constant off-time,
current mode step-down architecture. During normal opera-
tion, the top MOSFET is turned on each cycle when the
oscillator sets the SR latch and turned off when the main
current comparator I
CMP
resets the SR latch. While the top
MOSFET is off, the bottom MOSFET is turned on until either
the inductor current trips the current comparator I
REV
or the
beginning of the next cycle. The oscillator uses the equation:
t
VV
Vf
OFF
DCIN BAT
DCIN OSC
=
to set the bottom MOSFET on time. This activity is dia-
grammed in Figure 1.
The peak inductor current, at which I
CMP
resets the SR latch,
is controlled by the voltage on I
TH
. I
TH
is in turn controlled by
several loops, depending upon the situation at hand. The
average current control loop converts the voltage between
CSP and BAT to a representative current. Error amp CA2
OPERATIO
U
TGATE
OFF
ON
BGATE
INDUCTOR
CURRENT
t
OFF
TRIP POINT SET BY ITH VOLTAGE
ON
OFF
4006 F01
Figure 1
9
LTC4006
4006fa
OPERATIO
U
compares this current against the desired current programmed
by R
IMON
at the I
MON
pin and adjusts I
TH
until:
V
R
VV Ak
k
REF
IMON
CSP BAT
=
–.11 67 3
3
therefore,
I
V
R
A
k
R
CHARGE
REF
IMON SENSE
–. 11 67
3
The voltage at BAT is divided down by an internal resistor
divider and is used by error amp EA to decrease I
TH
if the
divider voltage is above the 1.19V reference. When the
charging current begins to decrease, the voltage at I
MON
will decrease in direct proportion. The voltage at I
MON
is
then given by:
VI R Ak
R
k
IMON CHARGE SENSE
IMON
=+µ
()
•.11 67 3
3
Table 1. Truth Table for LTC4006 Operation
MODE DCIN BAT VOLTAGE BAT CURRENT ACP/SHDN TIMER STATE CHG*
Shut Down by Low Adapter Voltage <BAT >UVLO Leakage LOW Reset HIGH
Conditioning a Depleted Battery >BAT <2.5V/Cell 10% Programmed HIGH Running LOW
Current
Normal Charging >BAT >2.5V/Cell Programmed HIGH Running LOW
Current
Input Current Limited Charging >BAT >2.5V/Cell Programmed HIGH Running LOW
Current
Charger Paused Due to Thermistor Out of Range >BAT X OFF HIGH Paused LOW or 25µA
(Faulted)
Shut Down by ACP/SHDN Pin >BAT X OFF Forced LOW Reset HIGH
Terminated by Low-Battery Fault (Note 1) >BAT <2.5V/Cell OFF HIGH >T/4 Stopped HIGH
(Faulted)
Top-Off Charging. C/10 is Latched >BAT V
FLOAT
OFF HIGH <T/4 After C/10 25µA
Comparator Trip.
Running
Timer is Reset by C/10 Comparator (Latched), >BAT V
FLOAT
OFF HIGH >T/4 After C/10 HIGH
then Terminates After 1/4 T Comparator Trip. (Waiting
Stopped for Restart)
Terminated by Expired Timer >BAT V
FLOAT
** OFF HIGH >T Stopped HIGH
(Waiting
for Restart)
Timer Defeated. (Low-Battery Conditioning Still X X X X X Forced LOW
Functional)
Shut Down by Undervoltage Lockout >BAT <UVL OFF HIGH Reset HIGH**
and <UVL
Timer Defeated Until V
BAT
> 3.9V/Cell >BAT 2.5V V
BAT
3.9V Programmed HIGH Running LOW
(V/Cell) Current
*Open Drain. High when used with pull-up resistor.
**Most probable condition, X = Don’t care
Note 1: If a depleted battery is inserted while the charger is in this state,
the charger must be reset to initiate charging.
The accuracy of V
IMON
will range from 0% to I
TOL
.
V
IMON
is plotted in Figure 2.
The amplifier CL1 monitors and limits the input current to
a preset level (100mV/R
CL
). At input current limit, CL1 will
decrease the I
TH
voltage, thereby reducing charging cur-
rent. When this condition is detected, the C/10 indicator will
Figure 2. V
IMON
vs I
CHARGE
I
CHARGE
(% OF MAXIMUM CURRENT)
0
0
V
IMON
(V)
0.2
0.4
0.6
0.8
4006 F02
1.0
1.2
20 40 60 80 100
1.19V
0.309V

LTC4006EGN-2#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management 4A, Simplified Li-Ion Charger for 3-Cell
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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