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CY2304SXC-2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
CY2304
Document Number: 38-07247 Rev. *O Page 4 of 17
Zero Delay and Skew Control
Figure 2. REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins
To close the feedback loop of the CY2304, the FBK pin can be driven from any of the four available output pins. The output driving
the FBK pin is driving a total load of 7 pF, with any additional load that it drives. The relative loading of this output (with respect to the
remaining outputs) can adjust the input-output delay. This is shown in Figure 2.
For applications requiring zero input-output delay, all outputs including the one providing feedback must be equally loaded. If
input-output delay adjustments are required, use the graph shown in Figure 2 to calculate loading differences between the feedback
output and remaining outputs.
For zero output-output skew, be sure to load outputs equally. For further information on using CY2304, refer to the application note
AN1234 - Understanding Cypress’s Zero Delay Buffers.
CY2304
Document Number: 38-07247 Rev. *O Page 5 of 17
Maximum Ratings
Supply voltage to ground potential ............. –0.5 V to +7.0 V
DC input voltage (except Ref) ........... –0.5 V to V
DD
+ 0.5 V
DC input voltage REF ...................................... –0.5 V to 7 V
Storage temperature ............................... –65 °C to +150 °C
Junction temperature ................................................ 150 °C
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2000 V
Operating Conditions
For CY2304SXC Commercial Temperature Devices
Parameter Description Min Max Unit
V
DD
Supply voltage 3.0 3.6 V
T
A
Operating temperature (ambient temperature) 0 70 °C
C
L
Load capacitance (below 100 MHz) – 30 pF
Load capacitance (from 100 MHz to 133 MHz) – 15 pF
C
IN
Input capacitance
[3]
–7pF
t
PU
Power-up time for all V
DD
s to reach minimum specified voltage (power ramps must
be monotonic)
0.05 50 ms
Electrical Characteristics
For CY2304SXC Commercial Temperature Devices
Parameter Description Test Conditions Min Max Unit
V
IL
Input LOW voltage – 0.8 V
V
IH
Input HIGH voltage 2.0 – V
I
IL
Input LOW current V
IN
= 0 V – 50.0 A
I
IH
Input HIGH current V
IN
= V
DD
– 100.0 A
V
OL
Output LOW voltage
[4]
I
OL
= 8 mA (-1, -2) – 0.4 V
V
OH
Output HIGH voltage
[4]
I
OH
= –8 mA (-1, -2) 2.4 – V
I
DD
(PD mode) Power-down supply current REF = 0 MHz – 12.0 A
I
DD
Supply current Unloaded outputs, 100 MHz REF, Select inputs
at V
DD
or GND
–45.0mA
Unloaded outputs, 66 MHz REF (-1, -2) – 32.0 mA
Unloaded outputs, 33 MHz REF (-1, -2) – 18.0 mA
Notes
3. Applies to both REF clock and FBK.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
CY2304
Document Number: 38-07247 Rev. *O Page 6 of 17
Switching Characteristics
For CY2304SXC Commercial Temperature Devices
Parameter
[5]
Name Test Conditions Min Typ Max Unit
t
1
Output frequency 30 pF load, all devices 10 – 100 MHz
t
1
Output frequency 15 pF load, -1, -2 devices 10 – 133.3 MHz
t
DC
Duty cycle
[6]
= t
2
t
1
(-1, -2)
Measured at 1.4 V,
F
OUT
= 66.66 MHz, 30-pF load
40.0 50.0 60.0 %
t
DC
Duty cycle
[6]
= t
2
t
1
(-2)
Measured at 1.4 V,
F
OUT
= 83.0 MHz, 15-pF load
40.0 50.0 60.0 %
t
DC
Duty cycle
[6]
= t
2
t
1
(-1, -2)
Measured at 1.4 V,
F
OUT
< 50 MHz, 15-pF load
45.0 50.0 55.0 %
t
3
Rise time
[6]
(-1, -2)
Measured between 0.8 V and 2.0 V,
30-pF load
– – 2.20 ns
t
3
Rise time
[6]
(-1, -2)
Measured between 0.8 V and 2.0 V,
15-pF load
– – 1.50 ns
t
4
Fall time
[6]
(-1, -2)
Measured between 0.8 V and 2.0 V,
30-pF load
– – 2.20 ns
t
4
Fall time
[6]
(-1, -2)
Measured between 0.8 V and 2.0 V,
15 pF load
– – 1.50 ns
t
5
Output-to-output skew on same
Bank (-1, -2)
[6]
All outputs equally loaded – – 200 ps
Output bank A to output bank B
skew (-1)
All outputs equally loaded – – 200 ps
Output bank A to output bank B
skew (-2)
All outputs equally loaded – – 400 ps
t
6
Skew, REF rising edge to FBK
rising edge
[6]
Measured at V
DD
/2 – 0 250 ps
t
7
Device-to-device skew
[6]
Measured at V
DD
/2 on the FBK pins
of devices
– 0 500 ps
t
J
Cycle-to-cycle jitter
[6]
(-1)
Measured at 66.67 MHz, loaded
outputs, 15-pF load
– 90 175 ps
Measured at 66.67 MHz, loaded
outputs, 30-pF load
– – 200 ps
Measured at 133.3 MHz, loaded
outputs, 15-pF load
– – 100 ps
t
J
Cycle-to-cycle jitter
[6]
(-2)
Measured at 66.67 MHz, loaded
outputs 30-pF load
– – 400 ps
Measured at 66.67 MHz, loaded
outputs 15-pF load
– – 375 ps
t
LOCK
PLL lock time
[6]
Stable power supply, valid clocks
presented on REF and FBK pins
– – 1.0 ms
Notes
5. All parameters are specified with loaded output.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

CY2304SXC-2

Mfr. #:
Buy CY2304SXC-2
Manufacturer:
Cypress Semiconductor
Description:
Clock Buffer 3.3VZDB COM
Lifecycle:
New from this manufacturer.
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