IR2161(
S
) & (PbF)
10 www.irf.com
across the CSD capacitor will vary from 0V if there is no
load to approximately 5V at maximum load.
This is provided that the correct value of current sense
resistor has been selected for the maximum rated load and
line voltage supply of the convertor. This should be 0.33
Ohm (0.5W) for a 100W system running from a 220-240V
AC line. (It should be noted that the RCS resistor value is
also critical for setting the limits for the shut down circuit)
In RUN mode the oscillator frequency will vary from
approximately 34kHz when VCSD is 5V (maximum load) to
70kHz when VCSD is 0V (no load). The result of this is that
if a lighter load, such as a single 35W lamp, is connected to
a 100W convertor, the frequency will shift upwards so that
the output voltage falls below the maximum that is desirable
for the lamp. This provides sufficient compensation for the
load to ensure that the lamp voltage will always be within
acceptable limits but does not require a complicated regulation
scheme involving feedback from the output.
An additional internal current source has been included to
discharge the external capacitor. This will provide
approximately 10% ripple at twice the line frequency if CSD
is 100nF.
The advantage of this is that during the line voltage half
cycle the oscillator frequency will vary by several kHz thus
spreading the EMI conducted and radiated emissions over
a range of frequencies and avoiding high amplitude peaks
at particular frequencies. In this way the filter components
used may be similar to those used in a common bipolar self-
oscillating system.
Figure 5, Voltage Compensation Circuit
Figure 6, VS voltage and CSD voltage.
In the above trace it can be seen that a leading edge phase
cut (triac) dimmer is connected at close to maximum
brightness. There is a short delay at the beginning of each
half cycle before the AC line voltage is switched to the
convertor. Dimming increases the ripple in the CSD voltage
and gives more modulation. This is an inherent effect that
causes no system problems.
The startup sequence of the CSD pin can be seen from the
point where VCC increases above the UVLO+ threshold.
Figure 7, Startup sequence of CSD.
This trace shows that after the CSD voltage has ramped up
through soft start, the system switches over to voltage com-
pensation mode and a ripple exists which allows the fre-
quency modulation (or dither) to occur. In this case the
CS
CSD
AV > 13
150K
12K
IR2161(S) & (PbF)
www.irf.com 11
convertor is close to maximum load. If the load is reduced,
the average level at which the ripple occurs (i.e. the DC
component) will be at a lower level.
Shut Down Circuit
The IR2161 contains a dual mode auto-resetting shutdown
circuit that detects both a short circuit or overload condition
in the convertor. The load current detected at the CS pin is
used to sense these conditions. If the output of the convertor
is short-circuited, a very high current will flow in the half
bridge and the system must shut down within a few mains
half cycles, otherwise the MOSFETs will rapidly be destroyed
due to excessive junction temperature. The internal CS pin
has an internal threshold (V
CSSC
). There also exists a lower
threshold so that if the voltage exceeds this level for more
than 50mS, the system will shut down.
A delay is included to prevent false tripping either due to
lamp inrush current at switch on (this current is still higher
than normal with the soft start operation) or transient
currents that may occur if an external triac based phase
cut dimmer is being used.
There also exists a lower threshold (V
CSOL
), which has a
much longer delay before it shuts down the system. This
provides the overload protection if an excessive number of
lamps is connected to the output or the output is short-
circuited at the end of a length of cable that has sufficient
resistance to prevent the current from being large enough
to trip the short circuit protection. Also under this condition
there is an excessive current in the half bridge that is
sufficient to cause heating and eventual failure but over a
longer period of time. The threshold for overload shutdown
is approximately 50% above maximum load with a delay of
approximately 0.5s. These timings are based on a current
waveform that has a sinusoidal envelope and a high
frequency square wave component with 50% duty cycle.
Both shutdown modes are auto resetting, which allows the
oscillator to start again approximately 1.5s after shutting
down. This is so that if the fault condition is removed the
system can start operating normally again without the line
voltage having to be switched off and back on again. It also
provides a good indication of overload to the end user as all
the lamps connected to the system will flash on and off
continuously if too many are connected.
The shut down circuit also uses the external CSD capacitor for
its timing functions. When the 0.5V threshold (V
CSOL
) is ex-
ceeded at CS the CSD is internally disconnected from the voltage
compensation circuit and connected to the shutdown circuit.
Figure 8, Shut Down Circuit.
The oscillator operates at minimum frequency when the
CSD capacitor is required for shutdown circuit timing.
During soft start or run mode, if the 0.5V threshold (V
CSOL
)
is exceeded the IR2161 charges CSD rapidly to approxi-
mately 5V (V
CSDOL
).
When the voltage at the CS input is greater than 0.5V, the
CSD capacitor is charged by current source I
OL
and when
the short circuit threshold of 1.2V is exceeded it is charged
by I
SC
as well. If 1.2V is exceeded CSD will charge from 5V
(V
CSDOL
) to 12V (V
CSDSD
), in approximately 50ms. When
0.5V is exceeded but 1.2V is not, CSD charges from 5V
(V
CSDOL
) to 12V (V
CSDSD
) in approximately 0.5s. It should
be remembered that, the timing accounts for the fact that
high frequency pulses with approximately 50% duty cycle
and a sinusoidal envelope appear at the CS pin.
The values of I
SC
and I
OL
take into account that only at the
peak of the mains will the comparator outputs go high and
effectively the capacitor will be charged in steps each line
half cycle. Once VCSD reaches 12V (V
CSDSD
), VCSD
discharges down to 2.4V (V
CSDRS
) and the system starts
up again. If the fault mode is still present, CSD starts
charging again.
If a fault is detected but goes away before CSD reaches
12V (V
CSDSD
), then CSD will discharge to 2.4V (V
CSDRS
)
and then the system will revert to compensation mode
without interruption of the output.
Following a shutdown, when the system starts up again
after the delay, the CSD capacitor will be internally switched
back to the voltage compensation circuit. However, if the
fault is still present the system will switch CSD back to the
shutdown circuit again.
1.2V
0.54V
Q
S
RQ
12V
2.5V
CSD
Enable OutputsCS
I_OL
I_SC
Shutdown Function
Overload Function
Switch
I_RESET
4V
IR2161(
S
) & (PbF)
12 www.irf.com
Figure 10, Overload Output Current.
In figures 9 and 10, trace (1) shows the half bridge
oscillations during both types of fault mode and trace (2)
shows the charging and discharging of the CSD capacitor.
The IR2161 can also be externally shut off by applying a
voltage above 9V (VCSLATCH) to the CS pin. This will
cause the system to go directly to a latched fault mode,
after a delay of approximately 1uS to avoid the possibility of
false tripping caused by transients. To restart the system, it
is necessary to cycle Vcc off and on.
In addition, any time Vcs exceeds VCSLATCH
(approximately half Vcc), this latching shutdown function
will be triggered and the system will remain in FAULT mode
until VCC is re-cycled.
The IR2161 also includes over temperature shutdown, which
latches the convertor off when the die temperature of the
IC exceeds 130-135°C. Experimental measurements reveal
that the die temperature will be no more than 20°C above
the ambient temperature at all operating frequencies inside
the convertor.
Calculating Rcs
The value of the current sense resistor Rcs is critical to
achieve correct operation in the IR2161 based Halogen
convertor.
Figure 11, Calculating RCS
Ignoring the output transformer we can assume for this
calculation that the load is connected from the half bridge to
the mid point of the two output capacitors and that the
voltage at this point will be half the DC bus voltage. The
RMS voltage of the DC bus is the same as that of the AC line
so we can see that the RMS voltage across the load shown
in Figure 8, will be half the RMS voltage of the line. The load
is the maximum rated load of the convertor. The current in
Rcs will be half the load current given by :
LOAD
RCS
VCS
DC Bus
Voltage
1/2 DC Bus
Voltage
VS
VCSpk
Figure 9, Short Circuit Output Current.

IR2161STRPBF

Mfr. #:
Manufacturer:
Infineon / IR
Description:
Gate Drivers Halogen Cnvrtr Cntrl IC
Lifecycle:
New from this manufacturer.
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