IR2161(
S
) & (PbF)
14 www.irf.com
Figure 12, ADT when VS slews from COM to VBUS
The above waveforms are typical, showing the operation
of the ADT circuit in either direction. In this case the design
could be optimized further by increasing the snubber ca-
pacitor to slightly increase the slew time, in order to ac-
count for the propagation delays in the system. Alterna-
tively an output transformer with a greater leakage induc-
tance can extend the period before the VS voltage turns
around and starts to go back the other way again.
The designer does not need to take into account parasitic
capacitances in the MOSFETs or leakage inductance in the
output transformer and fix the dead time accordingly.
The system can operate reliably down to dead times in the
order of 300nS, which should be low enough to
accommodate the output transformer leakage inductance
and parasitic MOSFET capacitances of a practical Halogen
convertor.
The slew rate can easily be increased, if necessary, by
adding a small snubber capacitor across the primary of the
transformer if necessary. However, should the snubber
capacitor be too large, it will prevent the VS voltage from
slewing all the way to the opposite rail. Consequently the
ADT function will be unable to operate, causing the IR2161
to revert to the default dead time of 1μS. Snubber capacitors
would normally be in the order of hundreds of pF.
When designing a halogen convertor it is desirable to optimize
the system at maximum load, where the conduction losses
of the power MOSFETs in the half-bridge will be at a
maximum. At lighter loads there may be hard switching if
the VS voltage is unable to slew all the way or it slews so
rapidly that the voltage begins to turn around again before
the IR2161 is able to switch on the relevant MOSFET in the
half bridge.
Such a situation is not desirable but may be acceptable at
lighter loads where the conduction losses are small.
With correct optimization of the output transformer and
surrounding circuit it is possible to achieve a design that
will not hard switch from 20% to 100% of the maximum
rated load of the system.
This system avoids the need for an external resistor to
program the dead time and contributes to the multi func-
tional nature of the CSD pin to the IR2161 being realized
with only 8 external pins
In any design when there is no load at the output, the VS
voltage will not slew and obviously the ADT circuit is not
able to function in this condition. In this case the dead time
will default to approximately 1μS, the maximum allowed by
the IC and there will be hard switching.
Although this will inevitably lead to some switching losses,
there are no conduction losses so the temperature rise of
the half bridge MOSFETs should not create a problem in this
case.
Dimming
Almost any Halogen convertor available can be dimmed by
an external phase cut dimmer that operates in trailing edge
mode. This means that at the beginning of the line voltage
half cycle, the switch inside the dimmer is closed and mains
voltage is supplied to the convertor allowing the convertor
to operate normally. At some point during the half cycle, the
switch inside the dimmer is opened and voltage is no longer
applied. The DC bus inside the convertor almost immediately
drops to 0V and the output is no longer present. In this way
bursts of high frequency output voltage are applied to the
lamp. The RMS voltage across the lamp will naturally vary
depending on the phase angle at which the dimmer switch
switches off. In this way the lamp brightness may easily
be varied from zero to maximum output.
