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IR1175
4
3
2
1
DTOUT2
VFLTRI
DTIN2
RADV1
VFLTR2
DTIN1
DTOUT1
RADV2
5
7
6
8
RVCO1
X1
RVCO2
X2
VSS
Q2*VDD
Q1
9
10
AVDD
UVSET
AVSS
RBIAS
IR1175S
(SSOP-20)
IR1175SS
SOIC (wide body)
Lead Definitions and Assignments
Symbol Description
AVDD Power - + 5 V
DC
to MOSFET drivers
Q1 Output - gate drive for Q1 power MOSFET
DTOUT1 Output - sets dead time for Q1 output - used with DTIN1
DTIN1 Input - sets dead time for Q1 - used with DTOUT1
RADV1 Output - sets lead time (advance) for Q1
VFLTR1 Output - PLL loop filter for Q1 output
RVCO1 Output - sets PLL center frequency for Q1 output
X1 Input - transformer input for Q1
VDD Power - +5 Vdc for internal logic
UVSET Input - sets UVLO+ If this pin is pulled below 1.25VDC externally, then both Q1 and Q2
outputs will be at Vss (disabled)
RBIAS Output - connected to 69.8K +/- 1% resistor - sets operating current
AVSS Ground for logic supply (AVDD)
X2 Input - transformer input for Q2
RVCO2 Output - sets PLL center frequency for Q2 output
VFLTR2 Output - PLL loop filter for Q2
RADV2 Output - sets lead time (advance) for Q2
DTIN2 Input - sets dead time for Q2 - used with DTOUT2
DTOUT2 Output - sets dead time for Q2 - used with DTIN2
VSS Ground for MOSFET driver supply (VDD)
Q2 Output - gate drive for Q2 power MOSFET
IR1175
PDIP
4
3
2
1
DTOUT2
VFLTRI
DTIN2
RADV1
VFLTR2
DTIN1
DTOUT1
RADV2
5
7
6
8
RVCO1
X1
RVCO2
X2
VSS
Q2
*VDD
Q1
9
10
AVDD
UVSET
AVSS
RBIAS
4
3
2
1
DTOUT2
VFLTRI
DTIN2
RADV1
VFLTR2
DTIN1
DTOUT1
RADV2
5
7
6
8
RVCO1
X1
RVCO2
X2
VSS
Q2*VDD
Q1
9
10
AVDD
UVSET
AVSS
RBIAS