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FN8175.4
September 23, 2009
Pinout
X9279
(14 LD TSSOP)
TOP VIEW
Pin Functions
Pin Descriptions
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for a
2-Wire slave device and is used to transfer data into and out
of the device. It receives device address, opcode, wiper
register address and data sent from an 2-Wire master at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock SCL.
It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open
drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
SERIAL CLOCK (SCL)
This input is used by 2-Wire master to supply 2-Wire serial
clock to the X9279.
DEVICE ADDRESS (A3 - A0)
The Address inputs A2 - A0 are used to set the least significant
3 bits of the 8-bit slave address, address pin A3 must be
connected to ground for proper operation. A match in the slave
address serial data stream must be made with the Address
input in order to initiate communication with the X9279. A
maximum of 8 devices may occupy the 2-Wire serial bus.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
GROUND (V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is
the system ground.
Other Pins
NO CONNECT
No connect pins should be left open. This pins are used for
Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP
)
The WP
pin when LOW prevents non-volatile writes to the
Data Registers.
Principles Of Operation
The X9279 is a integrated microcircuit incorporating a
resistor array and associated registers and counter and the
serial interface logic providing direct communication
between the host and the digitally controlled potentiometers.
This section provides detail description of the following:
Resistor Array Description
Serial Interface Description
Instruction and Register Description
Array Description
The X9279 is comprised of a resistor array (see Figure 1).
The array contains, in effect, 255 discrete resistive segments
that are connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R
W
)
output. Within each individual array only one switch may be
turned on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to
select, and enable, one of 256 switches (see Table 1).
The WCR may be written directly. These Data Registers can
the WCR can be read and written by the host system.
PIN
TSSOP SYMBOL FUNCTION
1 NC No Connect
2 A0 Device Address for 2-Wire bus
3 NC No Connect
4 A2 Device Address for 2-Wire bus
5 SCL Serial Clock for 2-Wire bus
6 SDA Serial Data Input/Output for 2-Wire bus
7V
SS
System Ground
8 WP Hardware Write Protect
9 A1 Device Address for 2-Wire bus
10 A3 Device Address for 2 wire-bus. Must be
connected to Ground
11 R
W
Wiper Terminal of the Potentiometer
12 R
H
High Terminal of the Potentiometer
13 R
L
Low Terminal of the Potentiometer
14 V
CC
System Supply Voltage
V
CC
R
L
V
SS
1
2
3
4
5
6
7
8
14
13
12
11
10
9
A0
R
W
SCL
A2
R
H
NC
NC
SDA
A3
WP
A1
X9279
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FN8175.4
September 23, 2009
Power-up and Down Recommendations.
There are no restrictions on the power-up or power-down
conditions of V
CC
and the voltages applied to the
potentiometer pins provided that V
CC
is always more
positive than or equal to V
H
, V
L
, and V
W
, i.e., V
CC
V
H
, V
L
,
V
W
. The V
CC
ramp rate specification is always in effect.
Serial Interface Description
Serial Interface
The X9279 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9279 will be
considered a slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (see
Figure 2.
Start Condition
All commands to the X9279 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9279 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met (see Figure 2).
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 2).
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9279 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9279 will
respond with a final acknowledge (see Figure 2).
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0 REGISTER 1
REGISTER 2 REGISTER 3
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
R
H
R
L
R
W
8 8
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN R
W
= R
L
IF WCR = FF[H] THEN R
W
= R
H
WIPER
(WCR)
BANK_0 Only
(DR0) (DR1)
(DR2)
(DR3)
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
R
X9279
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FN8175.4
September 23, 2009
Acknowledge Polling
The disabling of the inputs, during the internal non-volatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the non-volatile write command
the X9279 initiates the internal write cycle. ACK Polling
Sequence, Flow 1, can be initiated immediately. This
involves issuing the start condition followed by the device
slave address. If the X9279 is still busy with the write
operation no ACK will be returned. If the X9279 has
completed the write operation an ACK will be returned and
the master can then proceed with the next operation.
Flow 1: ACK Polling Sequence
Instruction and Register Description
Device Addressing: Identification Byte (ID and A)
The first byte sent to the X9279 from the host, following a CS
going HIGH to LOW, is called the Identification byte. The
most significant four bits of the slave address are a device
type identifier. The ID[3:0] bits is the device ID for the X9279;
this is fixed as 0101[B] (refer to Table 3).
The A[2:0] bits in the ID byte is the internal slave address.
The physical device address is defined by the state of the
A2 - A0 input pins. The slave address is externally specified
by the user. The X9279 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9279 to successfully
continue the command sequence. Only the device which
slave address matches the incoming device address sent by
the master executes the instruction. The A2 - A0 inputs can
be actively driven by CMOS input signals or tied to V
CC
or
V
SS
.
Instruction Byte (I)
The next byte sent to the X9279 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode I [2:0]. The RB and
RA bits point to one of the four Data Registers. P0 is the
POT selection; since the X9279 is single POT, the P0 = 0.
The format is shown in Table 4.
Register Bank Selection (RB, RA, P1, P0)
There are 16 registers organized into four banks. Bank 0 is
the default bank of registers. Only Bank 0 registers can be
used for Data Register to Wiper Counter Register
operations.
Banks 1, 2, and 3 are additional banks of registers (12 total)
that can be used for 2-Wire write and read operations. The
Data Registers in Banks 1, 2, and 3 cannot be used for direct
read/write operations between the Wiper Counter Register.
SCL FROM MASTER
1
89
DATA OUTPUT
ACKNOWLEDGE
FIGURE 2. ACKNOWLEGE RESPONSE FROM RECEIVER
FROM TRANSMITTER
FROM RECEIVER
DATA OUTPUT
START
Non-volatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Further
Operation?
Issue
Instruction
Issue STOP
No
Yes
Yes
Proceed
Issue STOP
No
Proceed
X9279

X9279TV14-2.7T1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC XDCP SGL 256TAP 100K 14-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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