PLL Frequency Synthesizer
Data Sheet
ADF4106
FEATURES
6.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (V
P
) allows extended
tuning voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios
GENERAL DESCRIPTION
The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise, digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A counter and B counter, and a dual-modulus prescaler (P/P + 1).
The A (6-bit) counter and B (13-bit) counter, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter) allows selectable REF
IN
frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
FUNCTIONAL BLOCK DIAGRAM
02720-001
CLK
DATA
LE
REF
IN
RF
IN
A
RF
IN
B
24-BIT INPUT
REGISTER
SD
OUT
AV
DD
DV
DD
CE
AGND
DGND
14-BIT
R COUNTER
R COUNTER
LATCH
22
14
FUNCTION
LATCH
A, B COUNTER
LATCH
FROM
FUNCTION
LATCH
PRESCALER
P/P + 1
N = BP + A
LOAD
LOAD
13-BIT
B COUNTER
6-BIT
A COUNTER
6
19
13
M3 M2 M1
MUX
SD
OUT
AV
DD
HIGH Z
MUXOUT
CPGND
R
SET
V
P
CP
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
REFERENCE
CHARGE
PUMP
CURRENT
SETTING 1
ADF4106
CPI3 CPI2 CPI1
CPI6 CPI5 CPI4
CURRENT
SETTING 2
Figure 1.
Rev. F Document Feedback
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ADF4106* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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EVALUATION KITS
ADF4106 Evaluation Board
DOCUMENTATION
Application Notes
AN-30: Ask the Applications Engineer - PLL Synthesizers
AN-807: Multicarrier WCDMA Feasibility
AN-808: Multicarrier CDMA2000 Feasibility
AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers
Data Sheet
ADF4106-DSCC: Military Data Sheet
ADF4106-EP: Enhanced Product Data Sheet
ADF4106: PLL Frequency Synthesizer Data Sheet
User Guides
UG-161: PLL Frequency Synthesizer Evaluation Board
UG-476: PLL Software Installation Guide
UG-582: Evaluating the EVAL-CN0290-SDPZ
SOFTWARE AND SYSTEMS REQUIREMENTS
ADF4106 FMC-SDP Interposer & Evaluation Board / Xilinx
KC705 Reference Design
BeMicro FPGA Project for ADF4106 with Nios driver
TOOLS AND SIMULATIONS
ADIsimPLL™
ADIsimRF
dt_ADF411x_Register_Configuration
ADF4106BCPZ IBIS Model
ADF4106BRUZ IBIS Model
REFERENCE DESIGNS
CN0290
REFERENCE MATERIALS
Product Selection Guide
RF Source Booklet
Technical Articles
Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 1
Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 3
Phase-Locked Loops for High-Frequency Receivers and
Transmitters - Part 2
DESIGN RESOURCES
ADF4106 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all ADF4106 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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ADF4106 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characterisitics ............................................................... 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
General Description ....................................................................... 10
Reference Input Section ............................................................. 10
RF Input Stage ............................................................................. 10
Prescaler (P/P +1) ....................................................................... 10
A Counter and B Counter ......................................................... 10
R Counter .................................................................................... 10
Phase Frequency Detector (PFD) and Charge Pump ............ 11
MUXOUT and Lock Detect ...................................................... 11
Input Shift Register .................................................................... 11
The Function Latch .................................................................... 17
The Initialization Latch ............................................................. 18
Applications ..................................................................................... 19
Local Oscillator for LMDS Base Station Transmitter ............ 19
Interfacing ................................................................................... 20
PCB Design Guidelines for Chip Scale Package .................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
4/15—Rev. E to Rev. F
Change to RF
IN
A to RF
IN
B Parameter, Table 3 .............................. 6
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
11/12—Rev. D to Rev. E
Changed EVAL-ADF4106EBZ1 to
EV-ADF4106SD1Z ...... Universal
Added RF
IN
A to RF
IN
B Parameter, Table 3 .................................... 6
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
9/11—Rev. C to Rev. D
Changes to Normalized Phase Noise Floor (PN
SYNTH
) Parameter,
Table 1 ................................................................................................ 4
Added Normalized 1/f Noise (PN
1_f
) Parameter and Endnote 12,
Table 1 ................................................................................................ 4
Changes to Ordering Guide .......................................................... 22
2/10—Rev. B to Rev. C
Changes to Figure 4 and Table 4 ..................................................... 6
Changes to Figure 12 ........................................................................ 8
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
6/05—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Figure 1 ........................................................................... 1
Changes to Table 1 ............................................................................. 3
Changes to Table 2 ............................................................................. 4
Changes to Table 3 ............................................................................. 5
Changes to Figure 3 and Figure 4 .................................................... 6
Changes to Figure 6 ........................................................................... 7
Changes to Figure 10 ......................................................................... 7
Deleted TPC 13 and TPC 14 ............................................................ 8
Changes to Figure 15 ......................................................................... 8
Changes to Figure 20 Caption ...................................................... 10
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
5/03—Rev. 0 to Rev. A
Edits to Specifications ....................................................................... 2
Edits to TPC 11 .................................................................................. 7
Updated Outline Dimensions ....................................................... 19
10/01—Revision 0: Initial Revision
Rev. F | Page 2 of 24

ADF4106BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Freq Synthesizer
Lifecycle:
New from this manufacturer.
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