Data Sheet ADN8831
Rev. A | Page 5 of 20
Parameter
1
Symbol Test Conditions/Comments Min Typ Max Unit
LOGIC Controls
Logic Low Output Voltage V
TMPGD, SYNCO, I
= 0 A 0.2 V
Logic High Output Voltage V
TMPGD, SYNCO, I
= 0 A V
− 0.2 V
Logic Low Input Voltage V
0.2 V
Output High Impedance V
= 5.0 V 35 Ω
Output Low Impedance V
= 5.0 V 20 Ω
Output High Impedance V
= 3.0 V 50 Ω
Output Low Impedance V
= 3.0 V 25 Ω
TEC CURRENT MEASUREMENT
ITEC Gain A
(V
– V
/2) / (V
− V
) 25 V/V
ITEC Output Range High V
No load V
− 0.05 V
ITEC Output Range Low V
0.05 V
ITEC Bias Voltage V
V
= V
= 0 1.10 1.20 1.30 V
Maximum ITEC Driving Current I
±1.5 mA
TEC VOLTAGE MEASUREMENT
VTEC Gain A
(V
– V
/2)/(V
− V
) 0.23 0.25 0.28 V/V
VTEC Output Range
2
V
V
= 5.0 V 0.05 2.5 V
VTEC Bias Voltage
2
V
V
= V
= 0 V 1.20 1.25 1.35 V
VTEC Output Load Resistance R
I
= 300 μA 35 Ω
VOLTAGE LIMIT
VLIM Gain A
(V
− V
)/V
5 V/V
VLIM Input Range
2
V
0 V
V
VLIM Input Current, Cooling
VLIM Input Current, Heating I
V
> V
/2 I
mA
VLIM Input Current Accuracy, Heating I
I
/I
0.8 1.0 1.18 A/A
CURRENT LIMIT
ILIMC Input Voltage Range V
V
/2 V
− 1 V
ILIMH Input Voltage Range V
0.1 V
/2 V
ILIMC Limit Threshold V
V
= 2.0 V, R
= 20 mΩ 1.98 2.0 2.02 V
ILIMH Limit Threshold V
V
= 0.5 V 0.48 0.5 0.52 V
TEMPERATURE GOOD
High Threshold V
IN2M tied to OUT2, V
= 1.5 V 1.55 1.60 V
Low Threshold V
IN2M tied to OUT2, V
= 1.5 V 1.40 1.45 V
1
Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).
2
Guaranteed by design or indirect test methods.
3
The ADN8831 does not work when the supply voltage is less than UVLO.
