CY8C4024LQI-S403 Datasheet CY8C4024LQI-S401, CY8C4025FNI-S402T, CY8C4024AZI-S413T | P10-P12

Document Number: 002-00123 Rev. *J Page 10 of 35

PSoC

4: PSoC 4000S Family

Datasheet

Power

The following power system diagram shows the set of power

supply pins as implemented for the PSoC 4000S. The system

has one regulator in Active mode for the digital circuitry. There is

no analog regulator; the analog circuits run directly from the V

input.

Figure 3. Power Supply Connections

There are two distinct modes of operation. In Mode 1, the supply

voltage range is 1.8 V to 5.5 V (unregulated externally; internal

regulator operational). In Mode 2, the supply range is1.8 V ±5%

(externally regulated; 1.71 to 1.89, internal regulator bypassed).

Mode 1: 1.8 V to 5.5 V External Supply

In this mode, the PSoC 4000S is powered by an external power

supply that can be anywhere in the range of 1.8 to 5.5 V. This

range is also designed for battery-powered operation. For

example, the chip can be powered from a battery system that

starts at 3.5 V and works down to 1.8 V. In this mode, the internal

regulator of the PSoC 4000S supplies the internal logic and its

output is connected to the V

CCD

pin. The VCCD pin must be

bypassed to ground via an external capacitor (0.1 µF; X5R

ceramic or better) and must not be connected to anything else.

Mode 2: 1.8 V ±5% External Supply

In this mode, the PSoC 4000S is powered by an external power

supply that must be within the range of 1.71 to 1.89 V; note that

this range needs to include the power supply ripple too. In this

mode, the VDD and VCCD pins are shorted together and

bypassed. The internal regulator can be disabled in the firmware.

Bypass capacitors must be used from VDDD to ground. The

typical practice for systems in this frequency range is to use a

capacitor in the 1-µF range, in parallel with a smaller capacitor

(0.1 µF, for example). Note that these are simply rules of thumb

and that, for critical applications, the PCB layout, lead induc-

tance, and the bypass capacitor parasitic should be simulated to

design and obtain optimal bypassing.

An example of a bypass scheme is shown in the following

diagram.

Figure 4. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active

Analog

Domain

VDDA

VSSA

VDDA

1.8 Volt

Regulator

Digital

Domain

VDDD

VSSD

VDDD

VCCD

PSoC 4000S

1.8V to 5.5V

0.1F

CCD

0.1F

Power supply bypass connections example

1.8V to 5.5V

0.1F

F

DDA

Document Number: 002-00123 Rev. *J Page 11 of 35

PSoC

4: PSoC 4000S Family

Datasheet

Development Support

The PSoC 4000S family has a rich set of documentation,

development tools, and online resources to assist you during

your development process. Visit www.cypress.com/go/psoc4 to

find out more.

Documentation

A suite of documentation supports the PSoC 4000S family to

ensure that you can find answers to your questions quickly. This

section contains a list of some of the key documents.

Software User Guide: A step-by-step guide for using

PSoC Creator. The software user guide shows you how the

PSoC Creator build process works in detail, how to use source

control with PSoC Creator, and much more.

Component Datasheets: The flexibility of PSoC allows the

creation of new peripherals (components) long after the device

has gone into production. Component data sheets provide all of

the information needed to select and use a particular component,

including a functional description, API documentation, example

code, and AC/DC specifications.

Application Notes: PSoC application notes discuss a particular

application of PSoC in depth; examples include brushless DC

motor control and on-chip filtering. Application notes often

include example projects in addition to the application note

document.

Technical Reference Manual: The Technical Reference Manual

(TRM) contains all the technical detail you need to use a PSoC

device, including a complete description of all PSoC registers.

The TRM is available in the Documentation section at

www.cypress.com/psoc4.

Online

In addition to print documentation, the Cypress PSoC forums

connect you with fellow PSoC users and experts in PSoC from

around the world, 24 hours a day, 7 days a week.

Tools

With industry standard cores, programming, and debugging

interfaces, the PSoC 4000S family is part of a development tool

ecosystem. Visit us at www.cypress.com/go/psoccreator for the

latest information on the revolutionary, easy to use PSoC Creator

IDE, supported third party compilers, programmers, debuggers,

and development kits.

Document Number: 002-00123 Rev. *J Page 12 of 35

PSoC

4: PSoC 4000S Family

Datasheet

Electrical Specifications

Absolute Maximum Ratings

Device Level Specifications

All specifications are valid for –40 °C  T

 85 °C and T

 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

Note

1. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended

periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.

Table 2. Absolute Maximum Ratings

[1]

Spec ID# Parameter Description Min Typ Max Units

Details/

Conditions

SID1 V

DDD_ABS

Digital supply relative to V

–0.5 – 6

–

SID2 V

CCD_ABS

Direct digital core voltage input relative

to V

–0.5 – 1.95 –

SID3 V

GPIO_ABS

GPIO voltage –0.5 – V

+0.5 –

SID4 I

GPIO_ABS

Maximum current per GPIO –25 – 25

–

SID5 I

GPIO_injection

GPIO injection current, Max for V

DDD

, and Min for V

< V

–0.5 – 0.5

Current injected

per pin

BID44 ESD_HBM

Electrostatic discharge human body

model

2200 – –

–

BID45 ESD_CDM

Electrostatic discharge charged device

model

500 – – –

BID46 LU Pin current for latch-up –140 – 140 mA –

Table 3. DC Specifications

Typical values measured at V

= 3.3 V and 25 °C.

Spec ID# Parameter Description Min Typ Max Units

Details/

Conditions

SID53 V

Power supply input voltage 1.8 – 5.5

Internally

regulated supply

SID255 V

Power supply input voltage (V

CCD

= V

DDA

)

1.71 – 1.89

Internally

unregulated

supply

SID54 V

CCD

Output voltage (for core logic) – 1.8 – –

SID55 C

EFC

External regulator voltage bypass – 0.1 –

µF

X5R ceramic or

better

SID56 C

EXC

Power supply bypass capacitor – 1 –

X5R ceramic or

better

Active Mode, V

= 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.

SID10 I

DD5

Execute from flash; CPU at 6 MHz – 1.2 2.0

–

SID16 I

DD8

Execute from flash; CPU at 24 MHz – 2.4 4.0 –

SID19 I

DD11

Execute from flash; CPU at 48 MHz – 4.6 5.9 –

Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)

SID22 I

DD17

C wakeup WDT, and Comparators on – 1.1 1.6 mA 6 MHz

SID25 I

DD20

C wakeup, WDT, and Comparators on – 1.4 1.9 12 MHz

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CY8C4024LQI-S403

Mfr. #:

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ARM Microcontrollers - MCU PSoC4

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