Document Number: 002-00123 Rev. *J Page 7 of 35
PSoC
®
4: PSoC 4000S Family
Datasheet
Pinouts
The following table provides the pin list for PSoC 4000S for the 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, and 25-ball CSP
packages. All port pins support GPIO. Pin 11 is a No-Connect in the 48-TQFP.
Table 1. PSoC 4000S Pin List
48-TQFP 32-QFN 24-QFN 25-CSP 40-QFN
Pin Name Pin Name Pin Name Pin Name Pin Name
28 P0.0 17 P0.0 13 P0.0 D1 P0.0 22 P0.0
29 P0.1 18 P0.1 14 P0.1 C3 P0.1 23 P0.1
30 P0.2 19 P0.2 24 P0.2
31 P0.3 20 P0.3 25 P0.3
32 P0.4 21 P0.4 15 P0.4 C2 P0.4 26 P0.4
33 P0.5 22 P0.5 16 P0.5 C1 P0.5 27 P0.5
34 P0.6 23 P0.6 17 P0.6 B1 P0.6 28 P0.6
35 P0.7 B2 P0.7 29 P0.7
36 XRES 24 XRES 18 XRES B3 XRES 30 XRES
37 VCCD 25 VCCD 19 VCCD A1 VCCD 31 VCCD
38 VSSD 26 VSSD 20 VSSD A2 VSS
39 VDDD 27 VDD 21 VDD A3 VDD 32 VDDD
40 VDDA 27 VDD 21 VDD A3 VDD 33 VDDA
41 VSSA 28 VSSA 22 VSSA A2 VSS 34 VSSA
42 P1.0 29 P1.0 35 P1.0
43 P1.1 30 P1.1 36 P1.1
44 P1.2 31 P1.2 23 P1.2 A4 P1.2 37 P1.2
45 P1.3 32 P1.3 24 P1.3 B4 P1.3 38 P1.3
46 P1.4 39 P1.4
47 P1.5
48 P1.6
1 P1.7 1 P1.7 1 P1.7 A5 P1.7 40 P1.7
2 P2.0 2 P2.0 2 P2.0 B5 P2.0 1 P2.0
3 P2.1 3 P2.1 3 P2.1 C5 P2.1 2 P2.1
4 P2.2 4 P2.2 3 P2.2
5 P2.3 5 P2.3 4 P2.3
6P2.4 5P2.4
7 P2.5 6 P2.5 6 P2.5
8 P2.6 7 P2.6 4 P2.6 D5 P2.6 7 P2.6
9 P2.7 8 P2.7 5 P2.7 C4 P2.7 8 P2.7
10 VSSD A2 VSS 9 VSSD
12 P3.0 9 P3.0 6 P3.0 E5 P3.0 10 P3.0
13 P3.1 10 P3.1 D4 P3.1 11 P3.1
14 P3.2 11 P3.2 7 P3.2 E4 P3.2 12 P3.2
16 P3.3 12 P3.3 8 P3.3 D3 P3.3 13 P3.3
Document Number: 002-00123 Rev. *J Page 8 of 35
PSoC
®
4: PSoC 4000S Family
Datasheet
Descriptions of the Pin functions are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ±5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
Alternate Pin Functions
Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD
pin, or a CapSense pin. The pin assignments are shown in the following table.
17 P3.4 14 P3.4
18 P3.5 15 P3.5
19 P3.6 16 P3.6
20 P3.7 17 P3.7
21 VDDD
22 P4.0 13 P4.0 9 P4.0 E3 P4.0 18 P4.0
23 P4.1 14 P4.1 10 P4.1 D2 P4.1 19 P4.1
24 P4.2 15 P4.2 11 P4.2 E2 P4.2 20 P4.2
25 P4.3 16 P4.3 12 P4.3 E1 P4.3 21 P4.3
Table 1. PSoC 4000S Pin List (continued)
48-TQFP 32-QFN 24-QFN 25-CSP 40-QFN
Pin Name Pin Name Pin Name Pin Name Pin Name
Port/
Pin
Analog Smart I/O Alternate Function 1 Alternate Function 2 Alternate Function 3 Deep Sleep 1 Deep Sleep 2
P0.0 lpcomp.in_p[0] tcpwm.tr_in[0] scb[0].spi_select1:0
P0.1 lpcomp.in_n[0] tcpwm.tr_in[1] scb[0].spi_select2:0
P0.2 lpcomp.in_p[1] scb[0].spi_select3:0
P0.3 lpcomp.in_n[1]
P0.4 wco.wco_in scb[1].uart_rx:0 scb[1].i2c_scl:0 scb[1].spi_mosi:1
P0.5 wco.wco_out scb[1].uart_tx:0 scb[1].i2c_sda:0 scb[1].spi_miso:1
P0.6 srss.ext_clk scb[1].uart_cts:0 scb[1].spi_clk:1
P0.7 scb[1].uart_rts:0 scb[1].spi_select0:1
P1.0 tcpwm.line[2]:1 scb[0].uart_rx:1 scb[0].i2c_scl:0 scb[0].spi_mosi:1
P1.1 tcpwm.line_compl[2]:1 scb[0].uart_tx:1 scb[0].i2c_sda:0 scb[0].spi_miso:1
P1.2 tcpwm.line[3]:1 scb[0].uart_cts:1 tcpwm.tr_in[2] scb[0].spi_clk:1
P1.3 tcpwm.line_compl[3]:1 scb[0].uart_rts:1 tcpwm.tr_in[3] scb[0].spi_select0:1
P1.4 scb[0].spi_select1:1
P1.5 scb[0].spi_select2:1
Document Number: 002-00123 Rev. *J Page 9 of 35
PSoC
®
4: PSoC 4000S Family
Datasheet
P1.6 scb[0].spi_select3:1
P1.7
P2.0 prgio[0].io[0] tcpwm.line[4]:0 csd.comp tcpwm.tr_in[4] scb[1].i2c_scl:1 scb[1].spi_mosi:2
P2.1 prgio[0].io[1] tcpwm.line_compl[4]:0 tcpwm.tr_in[5] scb[1].i2c_sda:1 scb[1].spi_miso:2
P2.2 prgio[0].io[2] scb[1].spi_clk:2
P2.3 prgio[0].io[3] scb[1].spi_select0:2
P2.4 prgio[0].io[4] tcpwm.line[0]:1 scb[1].spi_select1:1
P2.5 prgio[0].io[5] tcpwm.line_compl[0]:1 scb[1].spi_select2:1
P2.6 prgio[0].io[6] tcpwm.line[1]:1 scb[1].spi_select3:1
P2.7 prgio[0].io[7] tcpwm.line_compl[1]:1 lpcomp.comp[0]:1
P3.0 prgio[1].io[0] tcpwm.line[0]:0 scb[1].uart_rx:1 scb[1].i2c_scl:2 scb[1].spi_mosi:0
P3.1 prgio[1].io[1] tcpwm.line_compl[0]:0 scb[1].uart_tx:1 scb[1].i2c_sda:2 scb[1].spi_miso:0
P3.2 prgio[1].io[2] tcpwm.line[1]:0 scb[1].uart_cts:1 cpuss.swd_data scb[1].spi_clk:0
P3.3 prgio[1].io[3] tcpwm.line_compl[1]:0 scb[1].uart_rts:1 cpuss.swd_clk scb[1].spi_select0:0
P3.4 prgio[1].io[4] tcpwm.line[2]:0 tcpwm.tr_in[6] scb[1].spi_select1:0
P3.5 prgio[1].io[5] tcpwm.line_compl[2]:0 tcpwm.tr_in[7] scb[1].spi_select2:0
P3.6 prgio[1].io[6] tcpwm.line[3]:0 tcpwm.tr_in[8] scb[1].spi_select3:0
P3.7 prgio[1].io[7] tcpwm.line_compl[3]:0 tcpwm.tr_in[9] lpcomp.comp[1]:1
P4.0 csd.vref_ext scb[0].uart_rx:0 tcpwm.tr_in[10] scb[0].i2c_scl:1 scb[0].spi_mosi:0
P4.1 csd.cshieldpads scb[0].uart_tx:0 tcpwm.tr_in[11] scb[0].i2c_sda:1 scb[0].spi_miso:0
P4.2 csd.cmodpad scb[0].uart_cts:0 lpcomp.comp[0]:0 scb[0].spi_clk:0
P4.3 csd.csh_tank scb[0].uart_rts:0 lpcomp.comp[1]:0 scb[0].spi_select0:0
Port/
Pin
Analog Smart I/O Alternate Function 1 Alternate Function 2 Alternate Function 3 Deep Sleep 1 Deep Sleep 2

CY8C4024LQI-S403

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
ARM Microcontrollers - MCU PSoC4
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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