12
LTC3701
3701fa
C
IN
and C
OUT
Selection
The selection of C
IN
is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The control-
ler with the highest (V
OUT
)(I
OUT
) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (V
OUT
+ V
D
)/
(V
IN
+ V
D
). To prevent large voltage transients, a low ESR
capacitor sized for the maximum RMS current of one
channel must be used. The maximum RMS capacitor
current is given by:
C
I
VV
VVVV
IN
MAX
IN D
OUT D IN OUT
Required I
RMS
≈
+
+
()()
[]
–
/12
This formula has a maximum at V
IN
= 2V
OUT
+ V
D
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufactur-
ers’ ripple current ratings are often based on only 2000
hours of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. Due to the high operating frequency of the LTC3701,
ceramic capacitors can also be used for C
IN
. Always
consult the manufacturer if there is any question.
The benefit of the LTC3701 2-phase operation can be cal-
culated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse re-
sistance, battery resistance, and PC board trace resistance
losses are also reduced due to the reduced peak currents
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source imped-
ance of the power supply/battery is included in the effi-
ciency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common C
IN
(s). Separating the sources and C
IN
may pro-
duce undesirable voltage and current resonances at V
IN
.
A small (0.1µF to 1µF) bypass capacitor between the chip
V
IN
pin and ground, placed close to the LTC3701, is also
suggested. A 10Ω resistor placed between C
IN
(C1) and
the V
IN
pin provides further isolation between the two
channels.
The selection of C
OUT
is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (∆V
OUT
) is approximated by:
∆≈ +
V I ESR
fC
OUT RIPPLE
OUT
1
8
where f is the operating frequency, C
OUT
is the output
capacitance and I
RIPPLE
is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I
RIPPLE
increases with input voltage.
Low Supply Operation
Although the LTC3701 can function down to approximately
2V, the maximum allowable output current is reduced when
V
IN
decreases below 3V. Figure 5 shows the amount of
change as the supply is reduced down to 2V. Also shown
is the effect of V
IN
on V
REF
as V
IN
goes below 2.3V.
Setting Output Voltage
The LTC3701 output voltages are each set by an external
feedback resistive divider carefully placed across the
output capacitor (see Figure 6). The resultant feedback
signal is compared with an internal 0.8V reference by the
APPLICATIO S I FOR ATIO
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