15
LTC3701
3701fa
APPLICATIO S I FOR ATIO
WUUU
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (∆I
LOAD
)(ESR), where ESR is the effective series
resistance of
COUT
. ∆I
LOAD
also begins to charge or dis-
charge C
OUT
, which generates a feedback error signal. The
regulator loop then returns V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for over-
shoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
The I
TH
series R
C
-C
C
filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The I
TH
exter-
nal components shown in the Figure 1 circuit will provide
an adequate starting point for most applications. The
values can be modified slightly (from 0.2 to 5 times their
suggested values) to optimize transient response once the
final PC layout is done and the particular output capacitor
type and value have been determined. The output capaci-
tors need to be decided upon because the various types
and values determine the loop feedback factor gain and
phase. An output current pulse of 20% to 100% of full load
current having a rise time of 1µs to 10µs will produce
output voltage and I
TH
pin waveforms that will give a sense
of the overall loop stability. The gain of the loop will be
increased by increasing R
C
, and the bandwidth of the loop
will be increased by decreasing C
C
. The output voltage
settling behavior is related to the stability of the closed-
loop system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
LOAD
).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest amount of
time that the LTC3701 is capable of turning the top
MOSFET on and then off. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. The minimum on-time for the LTC3701 is
about 250ns. Low duty cycle and high frequency applica-
tions may approach this minimum on-time limit and care
should be taken to ensure that:
t
V
fV
ON MIN
OUT
IN
()
•
<
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3701 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3701. These items are illustrated graphically in the
layout diagram of Figure 10. Figure 11 illustrates the
current waveforms present in the various branches of the
2-phase regulators. Check the following in your layout:
1) Are the sense resistors and P-channel MOSFETs for the
two channels located within 1cm of each other with a
common connection at C
IN
? Do not attempt to split the
input decoupling for the two channels as it can cause a
large resonant loop.
